SBAA490A December   2021  – April 2022 PCM6120-Q1 , TAA5212 , TAC5111 , TAC5112 , TAC5211 , TAC5212 , TLV320ADC5120 , TLV320ADC6120

 

  1.   Trademarks
  2. 1Introduction
  3. 2Voice Activity Detector
    1. 2.1 VAD Configurations
    2. 2.2 VAD Parameters
  4. 3VAD Results
  5. 4Examples
  6. 5Related Documentation
  7. 6Revision History

2.1 VAD Configurations

Table 2-1 shows the different modes in which VAD can be operated.

Table 2-1 List of VAD Configuration
VAD Configuration Function, Description
User, Auto Auto: ADC power up and power down happens automatically on voice detection and no voice, respectively.
User: On detection of voice, interrupt is generated, user can initiate ADC power up and power down.
VAD channel Decides which channel is to be monitored for VAD activity.
VAD clock VAD needs to be run on internal clock or external clock.
VAD ON during recording This function decides if voice detection needs to be active when recording is in progress.
SDOUT interrupt SDOUT pin is enabled to support interrupt output when channel data is not being recorded.

User, Auto: VAD can be programmed by the user to be either in auto mode or user mode. There are 4 possible modes in which VAD can be programmed by the user.

0d = User initiated ADC power-up and ADC power-down: The user can initiate ADC power-up and ADC power-down based on the interrupt generated by the VAD algorithm.

1d = VAD interrupt based on ADC power up and ADC power down: This is the Auto mode, in which ADC is turned ON or OFF automatically based on the interrupt generated by the VAD algorithm.

As Table 2-2 shows, VAD mode selection is done using the VAD_mode[1:0] bit of VAD_CFG1 register (page = 0x01, address = 0x1E).

Table 2-2 VAD Mode Selection Using VAD_CFG1 Register
Bit Field Type Reset Description
7-6 VAD_MODE[1:0] R/W

00b

 Auto ADC power up and power down configuration selection.
0d = User initiated ADC power-up and ADC power down
1d = VAD interrupt based ADC power up and ADC power down
2d = VAD interrupt based ADC power up but user initiated ADC power down
3d = User initiated ADC power-up but VAD interrupt based ADC power down

VAD channel: This parameter decides which channel is to be monitored for VAD activity. Only one of the channels can be monitored for VAD activity at a time

As Table 2-3 shows, VAD channel selection is done using the VAD_CH_SEL[1:0] bit of VAD_CFG1 register (page = 0x01, address = 0x1E).

Table 2-3 VAD Channel Selection Using VAD_CFG1 Register
Bit Field Type Reset Description
5-4 VAD_CH_SEL[1:0] R/W

10b

 VAD channel select.
0d = Channel 1 is monitored for VAD activity
1d = Channel 2 is monitored for VAD activity
2d = Channel 3 is monitored for VAD activity
3d = Channel 4 is monitored for VAD activity

VAD clock: VAD can be run on either the internal oscillator clock or the external clock provided by the user. This external clock can be given on either the BCLK pin or the MCLK pin.

As Table 2-4 shows, VAD clock selection is done using the VAD_CLK_CFG[1:0] bit of VAD_CFG1 register (page = 0x01, address = 0x1E). If the user selects either 01b or 10b, then the frequency of external clock is selected using VAD_EXT_CLK_CFG[1:0] bit of VAD_CFG1 register (page = 0x01, address = 0x1E) as shown in Table 2-5.

Table 2-4 VAD Clock Selection Using VAD_CFG1 Register
Bit Field Type Reset Description
3-2 VAD_CLK_CFG[1:0] R/W

00b

 Clock select for VAD
0d = VAD processing using internal oscillator clock
1d = VAD processing using external clock on BCLK input
2d = VAD processing using external clock on MCLK input
3d = Custom clock configuration based on MST_CFG, CLK_SRC and CLKGEN_CFG registers in page 0
Table 2-5 VAD Clock Frequency Selection Using VAD_CFG1 Register
Bit Field Type Reset Description
1-0 VAD_EXT_CLK_CFG[1:0] R/W

00b

 Clock configuration using external clock for VAD.
0d = External clock is 3.072 MHz
1d = External clock is 6.144 MHz
2d = External clock is 12.288 MHz
3d = External clock is 18.432 MHz

VAD ON during recording: This parameter decides if voice activity needs to be detected when ADC is recording is on going or not. If this bit is enabled, then the VAD algorithm continues running when ADC recording is in progress to detect any voice activity.

As Table 2-6 shows, VAD ON during recording selection is done using the VAD_PD_DET_EN bit of VAD_CFG2 register (page = 0x01, address = 0x1F).

Table 2-6 VAD ON During Recording Selection Using VAD_CFG2 Register
Bit Field Type Reset Description
3 VAD_PD_DET_EN R/W 1b Enable ASI output data during VAD activity.
0d = VAD processing is not enabled during ADC recording
1d = VAD processing is enabled during ADC recording and VAD interrupts are generated as configured

SDOUT as interrupt: When ADC recording is not in progress, the SDOUT pin can be used for VAD interrupt. Setting this bit enables SDOUT to be used as the VAD interrupt pin.

As Table 2-7 shows, SDOUT as interrupt selection is done using the SDOUT_INT_CFG bit of VAD_CFG2 register (page = 0x01, address = 0x1F).

Table 2-7 SDOUT as Interrupt Selection Using VAD_CFG2 Register
Bit Field Type Reset Description
6 SDOUT_INT_CFG R/W

0b

 SDOUT interrupt configuration.
0d = SDOUT pin is not enabled for interrupt function
1d = SDOUT pin is enabled to support interrupt output when channel data in not being recorded