SBAA500A May   2021  – September 2021 PCM6020-Q1 , PCM6240-Q1 , PCM6260-Q1 , PCM6340-Q1


  1.   Trademarks
  2. 1Introduction
  3. 2Slave Mode Power Consumption with PLL Enabled
  4. 3Slave Mode Power Consumption with PLL Disabled
  5. 4Digital Microphone Power Consumption
  6. 5MICBIAS Power Consumption
  7. 6Settings for Lowest Power Consumption
  8. 7Revision History

Settings for Lowest Power Consumption

To minimize the power consumption of the PCM6xx0 devices, ensure that unused modules are disabled, use the lowest sampling rate, bit clock, and master clock needed by the application, and operate at the lowest AVDD and IOVDD supply voltage possible. The following list summarizes the settings and registers for lowest power operation:

  • Operate at the lowest supply voltage possible. IOVDD supports 1.8 V or 3.3 V supply, independently AVDD supports 3.3-V supply (AVDD and IOVDD can have different supply voltages).
    • Unused analog inputs, tie to analog ground.
    • Unused digital inputs, tie to digital ground.
    • Unused outputs, leave unconnected.
  • Disable unused ADC and PDM channels through the IN_CH_EN register.
  • Disable any unused output channel through the ASI_OUT_CH_EN register.
  • Disable MICBIAS power, if unused, through the PWR_CFG register.
  • Operate at the lowest sample rate possible.
  • Disable PLL, if the system supplies a low jitter master clock. Refer to Section 3 for a description of the settings to disable PLL.
  • Disable unused post-processing blocks:
    • Disable Biquad filters, if unused, through the BIQUAD_CFG bitfield of the DSP_CFG1 register.
    • Disable AGC, if unused in an active channel, through the CHx_AGCEN bitfield of the CHx_CFG0 register.
  • Select ultra-low latency over linear phase decimation filters, if the application allows, through the DECI_FILT bitfield of the DSP_CFG0 register.
  • Use the smallest word length allowed by the application through the ASI_WLEN bitfield of the ASI_CFG0 register.