SBAS629C October   2015  – April 2026 ADS9110

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements: Conversion Cycle
    7. 5.7  Timing Requirements: Asynchronous Reset, NAP, and PD
    8. 5.8  Timing Requirements: SPI-Compatible Serial Interface
    9. 5.9  Timing Requirements: Source-Synchronous Serial Interface (External Clock)
    10. 5.10 Timing Requirements: Source-Synchronous Serial Interface (Internal Clock)
    11. 5.11 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Converter Module
        1. 6.3.1.1 Sample-and-Hold Circuit
        2. 6.3.1.2 External Reference Source
        3. 6.3.1.3 Internal Oscillator
        4. 6.3.1.4 ADC Transfer Function
      2. 6.3.2 Interface Module
    4. 6.4 Device Functional Modes
      1. 6.4.1 RST State
      2. 6.4.2 ACQ State
      3. 6.4.3 CNV State
    5. 6.5 Programming
      1. 6.5.1 Data Transfer Frame
      2. 6.5.2 Interleaving Conversion Cycles and Data Transfer Frames
      3. 6.5.3 Data Transfer Protocols
        1. 6.5.3.1 Protocols for Configuring the Device
        2. 6.5.3.2 Protocols for Reading From the Device
          1. 6.5.3.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols
          2. 6.5.3.2.2 SPI-Compatible Protocols with Bus Width Options
          3. 6.5.3.2.3 Source-Synchronous (SRC) Protocols
            1. 6.5.3.2.3.1 Output Clock Source Options with SRC Protocols
            2. 6.5.3.2.3.2 Bus Width Options with SRC Protocols
            3. 6.5.3.2.3.3 Output Data Rate Options with SRC Protocols
      4. 6.5.4 Device Setup
        1. 6.5.4.1 Single Device: All multiSPI™ Options
        2. 6.5.4.2 Single Device: Minimum Pins for a Standard SPI Interface
        3. 6.5.4.3 Multiple Devices: Daisy-Chain Topology
        4. 6.5.4.4 Multiple Devices: Star Topology
    6. 6.6 Register Maps
      1. 6.6.1 Device Configuration and Register Maps
        1. 6.6.1.1 PD_CNTL Register (address = 010h)
        2. 6.6.1.2 SDI_CNTL Register (address = 014h)
        3. 6.6.1.3 SDO_CNTL Register (address = 018h)
        4. 6.6.1.4 DATA_CNTL Register (address = 01Ch)
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 ADC Input Driver
      2. 7.1.2 Input Amplifier Selection
      3. 7.1.3 Charge Kickback Filter
      4. 7.1.4 ADC Reference Driver
    2. 7.2 Typical Application
      1. 7.2.1 Data Acquisition (DAQ) Circuit for Lowest Distortion and Noise Performance With Differential Input
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 DAQ Circuit With FDA Input Driver and Single-Ended or Differential Input
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curves
  9. 8 Power-Supply Recommendations
    1. 8.1 Power-Supply Decoupling
    2. 8.2 Power Saving
      1. 8.2.1 NAP Mode
      2. 8.2.2 PD Mode
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Signal Path
      2. 9.1.2 Grounding and PCB Stack-Up
      3. 9.1.3 Decoupling of Power Supplies
      4. 9.1.4 Reference Decoupling
      5. 9.1.5 Differential Input Decoupling
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

3 Description

The ADS9110 is an 18-bit, 2MSPS, successive approximation register (SAR) analog-to-digital converter (ADC) with enhanced performance features. The high throughput enables developers to oversample the input signal to improve dynamic range and accuracy of the measurement. The ADS9120 is a pin-compatible, 16-bit, 2.5MSPS variant of the ADS9110.

The ADS9110 boosts analog performance while maintaining high-resolution data transfer by using TI’s enhanced SPI feature. Enhanced SPI enables the ADS9110 to achieve high throughput at lower clock speeds, thereby simplifying board layout and lowering system cost.

Enhanced SPI also simplifies the host clocking-in of data, thereby making the device ideal for applications involving FPGAs and DSPs. The ADS9110 is compatible with a standard SPI Interface. The ADS9110 has an internal data parity feature that can be appended to the ADC data output. ADC data validation by the host, using parity bits, improves system reliability.

The device supports JESD8-7A compliant I/Os, the extended industrial temperature range, and is offered in a space-saving, 4mm × 4mm, VQFN package.

SPI Interface Clock at Full Throughput
PART NUMBER(1) 3-WIRE SPI 3-WIRE ENHANCED-SPI
ADS9110 140MHz 40MHz
(1) For all features of the enhanced SPI, see the Interface Module section.



ADS9110 Ease of System Design with ADS9110 Ease of System Design with ADS9110