SBAS710A September   2016  – June 2017 ADS9120

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: Conversion Cycle
    7. 6.7  Timing Requirements: Asynchronous Reset, NAP, and PD
    8. 6.8  Timing Requirements: SPI-Compatible Serial Interface
    9. 6.9  Timing Requirements: Source-Synchronous Serial Interface (External Clock)
    10. 6.10 Timing Requirements: Source-Synchronous Serial Interface (Internal Clock)
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Converter Module
        1. 7.3.1.1 Sample-and-Hold Circuit
        2. 7.3.1.2 External Reference Source
        3. 7.3.1.3 Internal Oscillator
        4. 7.3.1.4 ADC Transfer Function
      2. 7.3.2 Interface Module
    4. 7.4 Device Functional Modes
      1. 7.4.1 RST State
      2. 7.4.2 ACQ State
      3. 7.4.3 CNV State
    5. 7.5 Programming
      1. 7.5.1 Data Transfer Frame
      2. 7.5.2 Interleaving Conversion Cycles and Data Transfer Frames
      3. 7.5.3 Data Transfer Protocols
        1. 7.5.3.1 Protocols for Configuring the Device
        2. 7.5.3.2 Protocols for Reading From the Device
          1. 7.5.3.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols
          2. 7.5.3.2.2 SPI-Compatible Protocols with Bus Width Options
          3. 7.5.3.2.3 Source-Synchronous (SRC) Protocols
            1. 7.5.3.2.3.1 Output Clock Source Options with SRC Protocols
            2. 7.5.3.2.3.2 Bus Width Options with SRC Protocols
            3. 7.5.3.2.3.3 Output Data Rate Options with SRC Protocols
      4. 7.5.4 Device Setup
        1. 7.5.4.1 Single Device: All multiSPI™ Options
        2. 7.5.4.2 Single Device: Minimum Pins for a Standard SPI Interface
        3. 7.5.4.3 Multiple Devices: Daisy-Chain Topology
        4. 7.5.4.4 Multiple Devices: Star Topology
    6. 7.6 Register Maps
      1. 7.6.1 Device Configuration and Register Maps
        1. 7.6.1.1 PD_CNTL Register (address = 010h)
        2. 7.6.1.2 SDI_CNTL Register (address = 014h)
        3. 7.6.1.3 SDO_CNTL Register (address = 018h)
        4. 7.6.1.4 DATA_CNTL Register (address = 01Ch)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 ADC Input Driver
      2. 8.1.2 Input Amplifier Selection
      3. 8.1.3 Charge Kickback Filter
      4. 8.1.4 ADC Reference Driver
    2. 8.2 Typical Application
      1. 8.2.1 Data Acquisition (DAQ) Circuit for Lowest Distortion and Noise Performance With Differential Input
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DAQ Circuit With FDA Input Driver and Single-Ended or Differential Input
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power-Supply Recommendations
    1. 9.1 Power-Supply Decoupling
    2. 9.2 Power Saving
      1. 9.2.1 NAP Mode
      2. 9.2.2 PD Mode
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Signal Path
      2. 10.1.2 Grounding and PCB Stack-Up
      3. 10.1.3 Decoupling of Power Supplies
      4. 10.1.4 Reference Decoupling
      5. 10.1.5 Differential Input Decoupling
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

9 Power-Supply Recommendations

The device has two separate power supplies: AVDD and DVDD. The internal circuits of the device operate on AVDD; DVDD is used for the digital interface. AVDD and DVDD can be independently set to any value within the permissible range.

9.1 Power-Supply Decoupling

The AVDD and DVDD supply pins cannot share the same decoupling capacitor. As shown in Figure 102, separate 1-μF ceramic capacitors are recommended. These capacitors avoid digital and analog supply crosstalk resulting from dynamic currents during conversion and data transfer.

ADS9120 Supply_bas629.gif Figure 102. Supply Decoupling

9.2 Power Saving

In normal mode of operation, the device does not power down between conversions, and therefore achieves a high throughput of 2.5 MSPS. However, the device offers two programmable low-power modes (NAP and PD) to reduce power consumption when the device is operated at lower throughput rates. Figure 103 shows comparative power consumption between the different modes of the device.

ADS9120 power_scaling_bas629.gif Figure 103. Power Consumption in Different Operating Modes

9.2.1 NAP Mode

In NAP mode, some of the internal blocks of the device power down to reduce power consumption in the ACQ state.

To enable NAP mode, set the NAP_EN bit in the PD_CNTL register. To exercise NAP mode, keep the CONVST pin high at the end of conversion process. The device then enters NAP mode at the end of conversion and continues in NAP mode until the CONVST pin is held high.

A CONVST falling edge brings the device out of NAP mode; however, the host controller can initiate a new conversion (CONVST rising edge) only after the tnap_wkup time has elapsed.

Figure 104 shows a typical conversion cycle with NAP mode enabled (NAP_EN = 1b).

ADS9120 ai_nap_conv_cycle_sbas629.gif Figure 104. NAP Enabled Conversion Cycle

The cycle time is given by Equation 17.

Equation 17. ADS9120 ai_eq_tcycle_sbas629.gif

At lower throughputs, cycle time (tcycle) increases but the conversion time (tconv) remains constant, and therefore the device spends more time in NAP mode, thus giving power scaling with throughput as shown in Figure 105.

ADS9120 D027_SBAS710.gif Figure 105. Power Scaling with Throughput with NAP Mode

9.2.2 PD Mode

The device also features a deep power-down mode (PD) to reduce the power consumption at very low throughput rates.

To enter PD mode:

  1. Write 069h to address 011h to unlock the PD_CNTL register.
  2. Set the PDWN bit in the PD_CNTL register. The device enters PD mode on the CS rising edge.

In PD mode, all analog blocks within the device are powered down. All register contents are retained and the interface remains active.

To exit PD mode:

  1. Reset the PDWN bit in the PD_CNTL register.
  2. The RVS pin goes high, indicating that the device has processed the command and has started coming out of PD mode. However, the host controller must wait for the tPWRUP time to elapse before initiating a new conversion.