SBAS728B November   2016  – May 2026 ADS8900B , ADS8902B , ADS8904B

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 LDO Module
      2. 6.3.2 Reference Buffer Module
      3. 6.3.3 Converter Module
        1. 6.3.3.1 Sample-and-Hold Circuit
        2. 6.3.3.2 Internal Oscillator
        3. 6.3.3.3 ADC Transfer Function
      4. 6.3.4 Interface Module
    4. 6.4 Device Functional Modes
      1. 6.4.1 RST State
      2. 6.4.2 ACQ State
      3. 6.4.3 CNV State
    5. 6.5 Programming
      1. 6.5.1 Output Data Word
      2. 6.5.2 Data Transfer Frame
      3. 6.5.3 Interleaving Conversion Cycles and Data Transfer Frames
      4. 6.5.4 Data Transfer Protocols
        1. 6.5.4.1 Protocols for Configuring the Device
        2. 6.5.4.2 Protocols for Reading From the Device
          1. 6.5.4.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols
          2. 6.5.4.2.2 SPI-Compatible Protocols with Bus Width Options
          3. 6.5.4.2.3 Source-Synchronous (SRC) Protocols
            1. 6.5.4.2.3.1 Output Clock Source Options with SRC Protocols
            2. 6.5.4.2.3.2 Bus Width Options With SRC Protocols
            3. 6.5.4.2.3.3 Output Data Rate Options With SRC Protocols
      5. 6.5.5 Device Setup
        1. 6.5.5.1 Single Device: All multiSPI Options
        2. 6.5.5.2 Single Device: Minimum Pins for a Standard SPI Interface
        3. 6.5.5.3 Multiple Devices: Daisy-Chain Topology
        4. 6.5.5.4 Multiple Devices: Star Topology
  8. 7 Register Maps
    1. 7.1 Device Configuration and Register Maps
      1. 7.1.1 PD_CNTL Register (address = 04h) [reset = 00h]
      2. 7.1.2 SDI_CNTL Register (address = 008h) [reset = 00h]
      3. 7.1.3 SDO_CNTL Register (address = 0Ch) [reset = 00h]
      4. 7.1.4 DATA_CNTL Register (address = 010h) [reset = 00h]
      5. 7.1.5 PATN_LSB Register (address = 014h) [reset = 00h]
      6. 7.1.6 PATN_MID Register (address = 015h) [reset = 00h]
      7. 7.1.7 PATN_MSB Register (address = 016h) [reset = 00h]
      8. 7.1.8 OFST_CAL Register (address = 020h) [reset = 00h]
      9. 7.1.9 REF_MRG Register (address = 030h) [reset = 00h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 ADC Reference Driver
      2. 8.1.2 ADC Input Driver
        1. 8.1.2.1 Charge-Kickback Filter
        2. 8.1.2.2 Input Amplifier Selection
    2. 8.2 Typical Application
      1. 8.2.1 Data Acquisition (DAQ) Circuit for Lowest Distortion and Noise Performance With Differential Input
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DAQ Circuit With FDA Input Driver and Single-Ended or Differential Input
      3. 8.2.3 Design Requirements
      4. 8.2.4 Detailed Design Procedure
      5. 8.2.5 Application Curves
  10. 9 Power-Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Signal Path
      2. 10.1.2 Grounding and PCB Stack-Up
      3. 10.1.3 Decoupling of Power Supplies
      4. 10.1.4 Reference Decoupling
      5. 10.1.5 Differential Input Decoupling
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

7.1.4 DATA_CNTL Register (address = 010h) [reset = 00h]

This register configures the contents of the 22-bit output data word (D[21:0]).

Figure 7-4 DATA_CNTL Register
76543210
0000FPAR_LOC[1:0]PAR_ENDATA_VAL
R-0bR-0bR-0bR-0bR/W-00bR/W-0bR/W-0b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-5 DATA_CNTL Register Field Descriptions
BitFieldTypeResetDescription
7-40R0000bReserved bits. Reads return 0000b.
3-2FPAR_LOC[1:0]R/W00bThese bits control the data span for calculating the FTPAR bit (bit D[0] in the output data word).
00b = D[0] reflects even parity calculated for 4 MSB
01b = D[0] reflects even parity calculated for 8 MSB
10b = D[0] reflects even parity calculated for 12 MSB
11b = D[0] reflects even parity calculated for 16 MSB
1PAR_ENR/W0b0b = Output data does not contain any parity information
  D[1] = 0
  D[0] = 0
1b = Parity information is appended to the LSB of the output data
  D[1] = Even parity calculated on bits D[21:2]
  D[0] = Even parity computed on selected number of MSB of D[21:2] as per FPAR_LOC[1:0] setting
See Figure 6-13 for further details of parity computation.
0DATA_VALR/W0bThese bits control bits D[21:2] of the output data word.
0b = 20-bit conversion output
1b = 20-bit contents of the fixed-pattern registers
See PATN CNTL for more details.