The host controller operates the device at the desired throughput by interleaving the conversion cycles and the data transfer frames.

The cycle time of the device, t_cycle, is the time difference between two consecutive CONVST rising edges provided by the host controller. The response time of the device, t_resp, is the time difference between the host controller initiating conversion C, and the host controller receiving the complete result for conversion C.

Figure 6-15 shows three conversion cycles: C, C + 1, and C + 2. Conversion C is initiated by a CONVST rising edge at time t = 0, and the conversion result becomes available for data transfer at t_conv. However, this result is loaded into the ODR only on the subsequent CS falling edge. This CS falling edge must be provided before the completion of conversion C + 1 (that is, before t_cycle + t_conv).

To achieve the rated performance specifications, the host controller must make sure that no digital signals toggle during the quiet acquisition time (t_{qt_acq}) and quiet aperture time (t_{d_cnvcap}). Any noise during t_{d_cnvcap} may negatively affect the result of the ongoing conversion, whereas any noise during t_{qt_acq} may negatively affect the result of the subsequent conversion.

Figure 6-15 Data Transfer Zones

This architecture allows for two distinct time zones (zone 1 and zone 2) to transfer data for each conversion. Zone 1 and zone 2 for conversion C are defined in Table 6-3.

Table 6-3 Data Transfer Zones Timing

ZONE	STARTING TIME	ENDING TIME
Zone 1 for conversion C
Zone 2 for conversion C

The response time includes the conversion time and the data transfer time, and thus is a function of the selected data transfer zone.

Figure 6-16 and Figure 6-17 illustrate interleaving of three conversion cycles (C, C + 1, and C + 2) with three data transfer frames (F, F + 1, and F + 2) in zone 1 and in zone 2, respectively.

Figure 6-16 Zone 1 Data Transfer

Figure 6-17 Zone 2 Data Transfer

To achieve cycle time t_cycle, the read time in zone 1 is given by Equation 5:

Equation 5.

For an optimal data transfer frame, Equation 5 results in an SCLK frequency given by Equation 6:

Equation 6.

Then, the zone 1 data transfer achieves a response time defined by Equation 7:

Equation 7.

At lower SCLK speeds, t_read-Z1 increases, resulting in slower response times and higher cycle times.

To achieve the same cycle time, t_cycle, the read time in zone 2 is given by Equation 8:

Equation 8.

For an optimal data transfer frame, Equation 8 results in an SCLK frequency given by Equation 9:

Equation 9.

Then, the zone 2 data transfer achieves a response time defined by Equation 10:

Equation 10.

Any increase in t_read-Z2 increases response time and may increase cycle time.

For a given cycle time, the zone 1 data transfer clearly achieves faster response time, but also requires a higher SCLK speed (as evident from Equation 5, Equation 6, and Equation 7); whereas, the zone 2 data transfer clearly requires a lower SCLK speed but has a slower response time (as evident from Equation 8, Equation 9, and Equation 10).