SBAS729C June   2016  – August 2026 ADS8920B , ADS8922B , ADS8924B

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 LDO Module
      2. 6.3.2 Reference Buffer Module
      3. 6.3.3 Converter Module
        1. 6.3.3.1 Sample-and-Hold Circuit
        2. 6.3.3.2 Internal Oscillator
        3. 6.3.3.3 ADC Transfer Function
      4. 6.3.4 Interface Module
    4. 6.4 Device Functional Modes
      1. 6.4.1 RST State
      2. 6.4.2 ACQ State
      3. 6.4.3 CNV State
    5. 6.5 Programming
      1. 6.5.1 Output Data Word
      2. 6.5.2 Data Transfer Frame
      3. 6.5.3 Interleaving Conversion Cycles and Data Transfer Frames
      4. 6.5.4 Data Transfer Protocols
        1. 6.5.4.1 Protocols for Configuring the Device
        2. 6.5.4.2 Protocols for Reading From the Device
          1. 6.5.4.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols
          2. 6.5.4.2.2 SPI-Compatible Protocols with Bus Width Options
          3. 6.5.4.2.3 Source-Synchronous (SRC) Protocols
            1. 6.5.4.2.3.1 Output Clock Source Options with SRC Protocols
            2. 6.5.4.2.3.2 Bus Width Options With SRC Protocols
            3. 6.5.4.2.3.3 Output Data Rate Options With SRC Protocols
      5. 6.5.5 Device Setup
        1. 6.5.5.1 Single Device: All multiSPI Options
        2. 6.5.5.2 Single Device: Minimum Pins for a Standard SPI
        3. 6.5.5.3 Multiple Devices: Daisy-Chain Topology
        4. 6.5.5.4 Multiple Devices: Star Topology
  8. 7 Register Maps
    1. 7.1 Device Configuration and Register Maps
      1. 7.1.1 PD_CNTL Register (address = 04h) [reset = 08h]
      2. 7.1.2 SDI_CNTL Register (address = 008h) [reset = 00h]
      3. 7.1.3 SDO_CNTL Register (address = 0Ch) [reset = 00h]
      4. 7.1.4 DATA_CNTL Register (address = 010h) [reset = 00h]
      5. 7.1.5 PATN_LSB Register (address = 014h) [reset = 00h]
      6. 7.1.6 PATN_MID Register (address = 015h) [reset = 00h]
      7. 7.1.7 PATN_MSB Register (address = 016h) [reset = 00h]
      8. 7.1.8 OFST_CAL Register (address = 020h) [reset = 00h]
      9. 7.1.9 REF_MRG Register (address = 030h) [reset = 00h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 ADC Reference Driver
      2. 8.1.2 ADC Input Driver
        1. 8.1.2.1 Charge-Kickback Filter
        2. 8.1.2.2 Input Amplifier Selection
    2. 8.2 Typical Application
      1. 8.2.1 Data Acquisition (DAQ) Circuit for Lowest Distortion and Noise Performance With Differential Input
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DAQ Circuit With FDA Input Driver and Single-Ended or Differential Input
      3. 8.2.3 Design Requirements
      4. 8.2.4 Detailed Design Procedure
      5. 8.2.5 Application Curves
    3. 8.3 Power-Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Signal Path
        2. 8.4.1.2 Grounding and PCB Stack-Up
        3. 8.4.1.3 Decoupling of Power Supplies
        4. 8.4.1.4 Reference Decoupling
        5. 8.4.1.5 Differential Input Decoupling
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

3 Description

The ADS8920B, ADS8922B, and ADS8924B (ADS892xB) belong to a family of pin-to-pin compatible, high-speed, single-channel, high-precision, 16-bit successive approximation register (SAR) based analog-to-digital convertors (ADCs) with an integrated reference buffer and integrated low-dropout regulator (LDO). The device family includes the ADS890xB (20-bit) and ADS891xB (18-bit) resolution variants.

The ADS892xB boost analog performance while maintaining high-resolution data transfer by using TI’s enhanced-SPI feature. Enhanced-SPI enables the ADS89xxB to achieve high throughput at lower clock speeds, thereby simplifying the board layout and lowering system cost. Enhanced-SPI also simplifies clocking-in of data, thereby making this device an excellent choice for applications involving FPGAs, DSPs. The ADS89xxB is compatible with a standard SPI.

Table 3-1 Package Information
DEVICE PACKAGE(1) PACKAGE SIZE(2)

ADS8920B

ADS8922B

ADS8924B

 RGE (VQFN, 24) 4mm × 4mm
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
ADS8920B ADS8922B ADS8924B Ease of System Design With ADS89xxB Integrated FeaturesEase of System Design With ADS89xxB Integrated Features