This device family features a multiSPI digital interface that allows the host controller to operate at slower SCLK speeds and still achieve the required throughput and response time. The multiSPI digital interface module offers three options to reduce the SCLK speed required for data transfer:

• Increase the width of the output data bus.
• Enable double data rate (DDR) transfer.
• Extended data transfer window, as shown in Figure 6-17.

These three options can be combined to achieve further reduction in SCLK speed.

There are various factors that limit the maximum SCLK frequency in a system.

Figure 6-18 shows the delays in the communication channel between the host controller and the device in a typical serial communication.

Figure 6-18 Delays in Serial Communication

For example, if t_{pcb_CK} and t_{pcb_SDO} are the delays introduced by the printed circuit board (PCB) traces for the serial clock and SDO signals, t_{d_CKDO} is the clock-to-data delay of the device, t_{d_ISO} is the propagation delay introduced by the digital isolator, and t_{su_h} is the setup time specification of the host controller, then the total delay in the path is given by Equation 12:

In a standard SPI protocol, the host controller and the device launch and capture data bits on alternate SCLK edges. Therefore, the t_{d_total_serial} delay must be kept to less than half of the SCLK duration. Equation 13 shows the fastest clock allowed by the SPI protocol:

Larger values of the t_{d_total_serial} delay restricts the maximum SCLK speed for the SPI protocol, resulting in higher read and response times, and can possibly limit the throughput.

Figure 6-19 shows a delay (t_{d_delcap}) introduced in the capture path (inside the host controller).

Figure 6-19 Delayed Capture

The total delay in the path modifies to Equation 14:

This reduction in total delay allows the SPI protocol to operate at higher clock speeds.

The multiSPI digital interface module offers two additional options to remove the restriction on the SCLK speed:

• Early data launch (EDL) mode of operation

  In EDL mode, the device launches the output data on SDO-x pin (or pins) half a clock earlier compared to the standard SPI protocol. Therefore, Equation 13 modifies to Equation 15:

  Equation 15. $f_{\text{ck-SPI}}\le \frac{1}{t_{\text{d\_total-serial}}}$

  The reduction in total delay allows the serial interface to operate at higher clock speeds.

• ADC-Clock-Master (source-synchronous) mode of operation

  As illustrated in Figure 6-20, in ADC-Clock-Master mode, the device provides a synchronous output clock (on the RVS pin) along with the output data (on the SDO-x pins).

  Figure 6-20 Delays in ADC-Clock-Master (Source-Synchronous) Mode

  For negligible values of t_{off_STRDO}, the total delay in the path for a source-synchronous data transfer, is given by Equation 16:

  Equation 16. $t_{\text{d\_total\_srcsync}}=t_{\text{pcb\_RVS}}-t_{\text{pcb\_SDO}}+t_{\text{su\_h}}$

  As shown by the difference between Equation 12 and Equation 16, using ADC-Clock-Master mode completely eliminates the effect of isolator delays (t_{d_ISO}) and clock-to-data delays (t_{d_CKDO}); typically, the largest contributors in the overall delay computation.

  Furthermore, the actual values of t_{pcb_RVS} and t_{pcb_SDO} do not matter. In most cases, the t_{d_total_srcsync} delay can be kept at a minimum by routing the RVS and SDO lines together on the PCB. Therefore, the ADC-Clock-Master mode allows the data transfer between the host controller and the device to operate at much higher SCLK speeds.