SBAS931B January   2019  – July 2022 ADS8353-Q1

PRODUCTION DATA  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Pin Configuration and Functions
  6. 6Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Thermal Information
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagram
    9. 6.9 Typical Characteristics
  7. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Reference
      2. 7.3.2 Analog Inputs
        1. 7.3.2.1 Analog Input: Full-Scale Range Selection
        2. 7.3.2.2 Analog Input: Single-Ended and Pseudo-Differential Configurations
      3. 7.3.3 Transfer Function
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Write to User-Programmable Registers
      3. 7.5.3 Data Read Operation
        1. 7.5.3.1 Reading User-Programmable Registers
        2. 7.5.3.2 Conversion Data Read
          1. 7.5.3.2.1 32-CLK, Dual-SDO Mode (CFR.B11 = 0, CFR.B10 = 0, Default)
          2. 7.5.3.2.2 32-CLK, Single-SDO Mode (CFR.B11 = 0, CFR.B10 = 1)
      4. 7.5.4 Low-Power Modes
        1. 7.5.4.1 STANDBY Mode
        2. 7.5.4.2 Software Power-Down (SPD) Mode
      5. 7.5.5 Frame Abort, Reconversion, or Short-Cycling
    6. 7.6 Register Maps
      1. 7.6.1 ADS8353-Q1 Registers
  8. 8Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input Amplifier Selection
      2. 8.1.2 Charge Kickback Filter
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
      1.      Mechanical, Packaging, and Orderable Information

7.6.1 ADS8353-Q1 Registers

Table 7-11 lists the memory-mapped registers for the ADS8353-Q1 registers. Consider any register offset addresses not listed in Table 7-11 as reserved locations and, therefore, do not modify the register contents.

Table 7-11 ADS8353-Q1 Registers
Offset Acronym Register Name Section
0h CFR CFR register Section 7.6.1.1
2h REFDAC REFDAC register Section 7.6.1.2

Complex bit access types are encoded to fit into small table cells. Table 7-12 shows the codes that are used for access types in this section.

Table 7-12 ADS8353-Q1 Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value

7.6.1.1 CFR Register (Offset = 0h) [reset = 0h]

CFR is shown in Figure 7-13 and described in Table 7-13.

Return to Summary Table.

Figure 7-13 CFR Register
15141312111098
WRITE_READ_CFR[3:0]RD_CLK_
MODE		RD_DATA_
LINES		INPUT_RANGERESERVED
R/W-0000bR/W-0bR/W-0bR/W-0bR/W-0b
76543210
INM_SELREF_SELSTANDBYRD_DATA_
FORMAT		0[3:0]
R/W-0bR/W-0bW-0bR/W-0bR/W-0000b
Table 7-13 CFR Register Field Descriptions
BitFieldTypeResetDescription
15-12WRITE_READ_CFR[3:0]R/W0000b

These bits select the user-programmable register.

0011b = Select this combination to read the CFR register

1000b = Select this combination to write to CFR register and enable bits 11:0

11RD_CLK_MODER/W0b

This bit must be set to 0 (default).

10RD_DATA_LINESR/W0b

This bit provides data line selection for the serial interface.

0b = Use SDO_A to output ADC_A data and SDO_B to output of ADC_B data (default)

1b = Use only SDO_A to output of ADC_A data followed by ADC_B data

9INPUT_RANGER/W0b

This bit selects the maximum input range for the ADC as a function of the reference voltage provided to the ADC. See the GUID-CBE1524F-2539-46D4-B41F-75B4A578EFEE.html#TITLE-SBAS931SBAS5566655 section for more details.

0b = FSR equals VREF

1b = FSR equals 2 × VREF

8RESERVEDR/W0b

This bit must be set to 0 (default).

7INM_SELR/W0b

This bit selects the voltage to be externally connected to the INM pin.

0b = INM must be externally connected to the GND potential (default)

1b = INM must be externally connected to the FSR_ADC_x / 2

6REF_SELR/W0b

This bit selects the ADC reference voltage source. See the GUID-17C4A85F-2C6C-4B5D-A11B-CB91BD0722AC.html#TITLE-SBAS931SBAS5564074 section for more details.

0b = Use external reference (default)

1b = Use internal reference

5STANDBYW0b

This bit is used by the device to enter or exit STANDBY mode. See the GUID-10091C13-2FE1-418B-B1F7-59449A1F4EFA.html#TITLE-SBAS931SBAS5564969 section for more details.

4RD_DATA_FORMATR/W0b

This bit selects the output data format.

0b = Output is in straight binary format (default)

1b = Output is in two's complement format

3-00[3:0]R/W0000b

These bits must be set to 0 (default).

7.6.1.2 REFDAC Register (Offset = 2h) [reset = 0h]

REFDAC is shown in Figure 7-14 and described in Table 7-14.

Return to Summary Table.

Figure 7-14 REFDAC Register
15141312111098
WRITE_READ_REFDAC[3:0]D[8:0]
R/W-0000bR/W-000000000b
76543210
D[8:0]RESERVED
R/W-000000000bR/W-000b
Table 7-14 REFDAC Register Field Descriptions
BitFieldTypeResetDescription
15-12WRITE_READ_REFDAC[3:0]R/W0000b

These bits select the configurable register address.
1001 = Select this combination to write to the REFDAC_A register
1010 = Select this combination to write to the REFDAC_B register

11-3D[8:0]R/W000000000b

Data to program the individual DAC output voltage.
These bits are valid only for bits 15:12 = 1001 or bits 15:12 = 1010.
Table 7-15 shows the relationship between the REFDAC_x programmed value and the DAC_x output voltage.

2-0RESERVEDR/W000b

This bit must be set to 0 (default).

Table 7-15 REFDAC Settings
REFDAC_x VALUE (Bits 11:3 in Hex)B[2:0]Typical DAC_x OUPTUT VOLTAGE (V)#SBAS5574534
1FF (default)0002.5000
1FE0002.4989
1FD0002.4978
———
1D70002.45
———
1AE0002.40
———
1860002.35
———
15D0002.30
———
1340002.25
———
10C0002.20
———
0E30002.15
———
0BA0002.10
———
0910002.05
———
0690002.00
———
064 to 000000Do not use
(1) Actual output voltage may vary by a few millivolts from the specified value. To obtain the desired output voltage, TI recommends starting with the specified register setting and then experimenting with five codes on either side of the specified register setting.