SBAS932A March   2024  – February 2026 DAC39RF10-SEP , DAC39RF10-SP , DAC39RFS10-SEP , DAC39RFS10-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI and FRI Timing Diagrams
    11. 6.11 Typical Characteristics: Bandwidth and DC Linearity
    12. 6.12 Typical Characteristics: Single Tone Spectra
    13. 6.13 Typical Characteristics: Dual Tone Spectra
    14. 6.14 Typical Characteristics: Noise Spectral Density
    15. 6.15 Typical Characteristics: Power Dissipation and Supply Currents
    16. 6.16 Typical Characteristics: Linearity Sweeps
    17. 6.17 Typical Characteristics: Modulated Waveforms
    18. 6.18 Typical Characteristics: Phase and Amplitude Noise
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RTZ Mode
        3. 7.3.1.3 RF Mode
        4. 7.3.1.4 DES Mode
      2. 7.3.2 DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3 DEM and Dither
      4. 7.3.4 Offset Adjustment
      5. 7.3.5 Clocking Subsystem
        1. 7.3.5.1 SYSREF Frequency Requirements
        2. 7.3.5.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      6. 7.3.6 Digital Signal Processing Blocks
        1. 7.3.6.1 Digital Upconverter (DUC)
          1. 7.3.6.1.1 Interpolation Filters
          2. 7.3.6.1.2 Numerically Controlled Oscillator (NCO)
            1. 7.3.6.1.2.1 Phase-Continuous NCO Update Mode
            2. 7.3.6.1.2.2 Phase-coherent NCO Update Mode
            3. 7.3.6.1.2.3 Phase-sync NCO Update Mode
            4. 7.3.6.1.2.4 NCO Synchronization
              1. 7.3.6.1.2.4.1 JESD204C LSB Synchronization
            5. 7.3.6.1.2.5 NCO Mode Programming
          3. 7.3.6.1.3 Mixer Scaling
        2. 7.3.6.2 Channel Bonder
        3. 7.3.6.3 DES Interpolator
      7. 7.3.7 JESD204C Interface
        1. 7.3.7.1  Deviation from JESD204C Standard
        2. 7.3.7.2  Transport Layer
        3. 7.3.7.3  Scrambler and Descrambler
        4. 7.3.7.4  Link Layer
        5. 7.3.7.5  Physical Layer
        6. 7.3.7.6  Serdes PLL Control
        7. 7.3.7.7  Serdes Crossbar
        8. 7.3.7.8  Multi-Device Synchronization and Deterministic Latency
          1. 7.3.7.8.1 Programming RBD
        9. 7.3.7.9  Operation in Subclass 0 Systems
        10. 7.3.7.10 Link Reset
      8. 7.3.8 Alarm Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 DUC and DDS Modes
      2. 7.4.2 JESD204C Interface Modes
        1. 7.4.2.1 JESD204C Interface Modes
        2. 7.4.2.2 JESD204C Format Diagrams
          1. 7.4.2.2.1 16-bit Formats
          2. 7.4.2.2.2 12-bit Formats
          3. 7.4.2.2.3 8-bit Formats
      3. 7.4.3 NCO Synchronization Latency
      4. 7.4.4 Data Path Latency
    5. 7.5 Programming
      1. 7.5.1 Using the Standard SPI Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Serial Interface Protocol
        6. 7.5.1.6 Streaming Mode
      2. 7.5.2 Using the Fast Reconfiguration Interface
  9. 8 SPI Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Startup Procedure for DUC/Bypass Mode
      2. 9.1.2 Startup Procedure for DDS Mode
      3. 9.1.3 Understanding Dual Edge Sampling Modes
      4. 9.1.4 Eye Scan Procedure
      5. 9.1.5 Pre/Post Cursor Analysis Procedure
      6. 9.1.6 Sleep and Disable Modes
      7. 9.1.7 Radiation Environment Recommendations
        1. 9.1.7.1 SPI Programming
        2. 9.1.7.2 JESD204C Reliability
        3. 9.1.7.3 NCO Reliability
          1. 9.1.7.3.1 NCO Frequency and Phase Correction (Strategy #1)
          2. 9.1.7.3.2 NCO Frequency Correction (Strategy No. 2)
    2. 9.2 Typical Application
      1. 9.2.1 S-Band Radar Transmitter
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Detailed Clocking Subsystem Design Procedure
        1. 9.2.4.1 Example 1: SWAP-C Optimized
        2. 9.2.4.2 Example 2: Improved Phase Noise LMX2820 with External VCO
        3. 9.2.4.3 Example 3: Discrete Analog PLL for Best DAC Performance
        4. 9.2.4.4 10GHz Clock Generation
      5. 9.2.5 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Up and Down Sequence
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines and Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

9.2.5 Application Curves

The radar chip waveform used for testing is a non-linear frequency modulated (NLFM) pulse, lasting 4096 samples at the 250MSPS complex input rate. At baseband, the frequency ramps from -100MHz to + 100MHz, following a frequency ramp curve developed by Price and shown in Equation 6 [Price R. Chebyshev Low Pulse Compression Sidelobes via a Nonlinear FM. National Radio Science Meeting of URSI; PortSaid, Egypt: 1979.] with T = 4096 samples, B = 0.8, Bl = 0.5611 and Bc = 0.238.

Equation 6. ff,Bl, Bc=B×t-T2T×Bl+Bc1-4t-T22T2

The NLFM Chirp frequency ramp is shown in Figure 9-13, complex time domain baseband waveform inFigure 9-14, baseband frequency spectrum in Figure 9-15 and auto-correlation in Figure 9-16.

DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP NLFM Frequency RampFigure 9-13 NLFM Frequency Ramp
DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP Digital Spectrum for NLFM ChirpFigure 9-15 Digital Spectrum for NLFM Chirp
DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP Complex Time Domain of NLFM Chirp (Red = real, Black = imag)Figure 9-14 Complex Time Domain of NLFM Chirp (Red = real, Black = imag)
DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP Auto-correlation of NLFM ChirpFigure 9-16 Auto-correlation of NLFM Chirp

The output spectra for the NLFM Chirp at 3.2GHz is shown in Figure 9-17. The largest spur is the duty-cycle image at 4.8GHz, which is suppressed 50dB. Figure 9-18 shows a 1GHz span centered at 3.2GHz. The interpolation filters confine the output spectrum to a 250MHz wide band at 3.2GHz. The spectra purity of the 200MHz is shown with a full scale tone in Figure 9-19. The largest spurs are ≅ 80dBc at 3.16GHz, which is the 4th harmonic (aliased back into 1st Nyquist zone), and the 6th harmonic at ≅ 86dBc.

DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP NLFM Chirp Output Spectra Across0 - 8GHzFigure 9-17 NLFM Chirp Output Spectra Across
0 - 8GHz
DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP In Band Single Tone Frequency Spectra with fOUT = 3.211GHzFigure 9-19 In Band Single Tone Frequency Spectra with fOUT = 3.211GHz
DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP NLFM Chirp Output Spectra Across1GHzFigure 9-18 NLFM Chirp Output Spectra Across
1GHz