SBASA01B September   2020  – March 2022 ADC3660

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - Power Consumption
    6. 6.6 Electrical Characteristics - DC Specifications
    7. 6.7 Electrical Characteristics - AC Specifications
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Analog Input Termination and DC Bias
            1. 8.3.1.2.2.1 AC-Coupling
            2. 8.3.1.2.2.2 DC-Coupling
        3. 8.3.1.3 Auto-Zero Feature
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Single Ended vs Differential Clock Input
        2. 8.3.2.2 Signal Acquisition Time Adjust
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 DDC MUX
        2. 8.3.4.2 Digital Filter Operation
          1. 8.3.4.2.1 FS/4 Mixing with Real Output
        3. 8.3.4.3 Numerically Controlled Oscillator (NCO) and Digital Mixer
        4. 8.3.4.4 Decimation Filter
        5. 8.3.4.5 SYNC
        6. 8.3.4.6 Output Formatting with Decimation
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 SDR Output Clocking
        2. 8.3.5.2 Output Data Format
        3. 8.3.5.3 Output Formatter
        4. 8.3.5.4 Output Bit Mapper
        5. 8.3.5.5 Output Interface/Mode Configuration
          1. 8.3.5.5.1 Configuration Example
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 Power Down Options
      3. 8.4.3 Digital Channel Averaging
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration using the SPI interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Maps
      1. 8.6.1 Detailed Register Description
  9. 9 Application and Implementation
    1. 9.1 Typical Application
      1. 9.1.1 Design Requirements
      2. 9.1.2 Detailed Design Procedure
        1. 9.1.2.1 Input Signal Path
        2. 9.1.2.2 Sampling Clock
        3. 9.1.2.3 Voltage Reference
      3. 9.1.3 Application Curves
    2. 9.2 Initialization Set Up
      1. 9.2.1 Register Initialization During Operation
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Support Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

8.3.5.5 Output Interface/Mode Configuration

The following sequence summarizes all the relevant registers for changing the output interface and/or enabling the decimation filter. Steps 1 and 2 must come first since the E-Fuse load reset the SPI writes, the remaining steps can come in any order.

Table 8-9 Configuration steps for changing interface or decimation
STEPFEATUREADDRESSDESCRIPTION
1Output Interface0x07Select the output interface bit mapping depending on resolution and output interface.
Output Resolution2-wire1-wire1/2-wire
14-bit, 18-bit0x2B0x6C0x8D
16-bit, 20-bit0x4B
20x13Load the output interface bit mapping using the E-fuse loader (0x13, D0). Program register 0x13 to 0x01, wait ~ 1ms so that bit mapping is loaded properly followed by 0x13 0x00
30x0A/B/CWhen changing the output interface bit mapper (0x07), the CMOS output buffer register has to be configured again.
40x18When changing the output interface bit mapper (0x07), the DCLKIN EN bit (D4) has to be set again.
50x19Configure the FCLK frequency based on bypass/decimation and number of lanes used.
Bypass/DecSCMOSFCLK SRC
(D7)		FCLK DIV
(D4)		TOG FCLK
(D0)
Bypass/ Real Decimation2-wire010
1-wire000
1/2-wire000
Complex Decimation2-wire100
1-wire100
1/2-wire001
60x1BSelect the output interface resolution using the bit mapper (D5-D3).
70x1FWhen changing the output interface bit mapper (0x07), the DCLKIN EN bit (D6) and DCLK OB EN (D4) have to be set again.
80x20
0x21
0x22		Select the FCLK pattern for decimation for proper duty cycle output of the frame clock.
Output Resolution2-wire1-wire1/2-wire
Real Decimation14-bituse default0xFE000use default
16-bit0xFF000
18-bit0xFF800
20-bit0xFFC00
Complex Decimation14-bit0xFFFFF0xFFFFF
16-bit
18-bit
20-bit
90x39..0x60
0x61..0x88		Change output bit mapping for chA and chB if desired. This works also with the default interface selection.
10Decimation Filter0x24Enable the decimation filter
110x25Configure the decimation filter
120x2A/B/C/D
0x31/2/3/4		Program the NCO frequency for complex decimation (can be skipped for real decimation)
130x27
0x2E		Configure the complex output data stream (set both bits to 0 for real decimation)
SCMOSOP-Order (D4)Q-Delay (D3)
2-wire10
1-wire01
1/2-wire11
140x26Set the mixer gain and toggle the mixer reset bit to update the NCO frequency.