SBAU363A February   2021  – March 2022 PCM1820 , PCM1820-Q1 , PCM1821 , PCM1821-Q1 , PCM1822 , PCM1822-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Power Supply
  4. 3Hardware Configuration
  5. 4PCM182xEVM /PCM182xQ1EVM Inputs
    1. 4.1 Onboard Microphone Inputs
    2. 4.2 Line Inputs
  6. 5Layer Plots
  7. 6Schematics
  8. 7Bill of Materials
  9. 8Revision History

3 Hardware Configuration

The format of the audio data and the operating mode of the ADC are controlled by the following pins: MD0, MD1, MSZ, and FMT0. These signals are referenced to IOVDD and can be set to high (1) or low (0). If no shunt is installed, then a 47-kΩ pulldown resistor will set the pin low so that the ADC remains in a defined state. Table 3-1 shows the header numbers and their pin functions and Table 3-2 , Table 3-2 and , Table 3-2 show the possible modes and output formats. The MSZ pin selects whether the device is a master or a slave on the audio bus. When MSZ is pulled high, the device is in master mode and MD1 becomes an input for MCLK. A shunt connecting J19 to the center pin of J18 will route the MCLK signal provided on J8 to the MD1 pin on the ADC to allow for easy interfacing with audio measurement equipment.

Table 3-1 PCM182xEVM /PCM182xQ1EVM Headers and Jumpers
DesignatorFunction
J1Differential line/mic input 1
J2Differential line/mic input 2
J4MICBIAS Selection
J5IOVDD-SYS voltage Selection (1.8V or 3.3V)
J6+5V input
J7AC-MB Connector
J8Audio Serial Interface header
J9Connect AVDD to onboard 3.3V regulator
J10Connect IOVDD to onboard regulator
J11Connect MICBIAS to onboard MIC2
J12Connect MIC2 OUT+ to ADC IN2P
J13MSZ select
J14Connect MICBIAS to onboard MIC1
J15Connect MIC1 OUT+ to ADC IN1P
J16Connect MIC1 OUT- to ADC IN1M
J17MD0 select
J18MD1 select
J19MCLK to MD1
J20FMT0 select
J21Connect MIC2 OUT- to ADC IN2M
J22IN2M capacitor bypass
J23IN1P capacitor bypass
J24IN2P capacitor bypass
J25IN1M capacitor bypass
Table 3-2 PCM182xEVM /PCM182xQ1EVM MD0 Modes

MD0 Modes

MD0MSZ (0 = Slave, 1 = Master)MD0 Functional Mode
00Linear phase filters are used for the decimation in slave mode. For master mode, the device always use linear phase filters for the decimation.
01System clock with frequency 256 × fS connected to the MD1 pin as MCLK
10System clock with frequency 512 × fS connected to the MD1 pin as MCLK
11Low latency filters are used for the decimation in slave mode. For master mode, the device always use linear phase filters for the decimation.
Table 3-3 PCM182xEVM /PCM182xQ1EVM MD1 Modes
MD1 Modes
MD1MSZ (0 = Slave, 1 = Master)MD0 Functional Mode
00DRE Disabled
10The DRE is enabled with DRE_LVL = –36 dB and DRE_MAXGAIN = 24 dB
MCLK1MCLK input in master mode
Table 3-4 PCM182xEVM /PCM182xQ1EVM Audio Output Format
Audio Output Data Format
FMT0Audio Serial Interface Format
02-channel output with inter IC sound (I2S) mode
12-channel output with time division multiplexing (TDM) mode

All hardware pins are tied low by default, placing the device in slave mode with a linear phase filter, DRE disabled, and 2-channel I2S audio output. Note that DRE is not supported for PCM1821/PCM1821-Q1 and only applies to PCM1820/PCM1822/PCM1820-Q1/PCM1822-Q1. For more information on the operating modes of the PCM182x device, see the PCM182x Stereo Channel, 32-Bit, 192-kHz, Burr-Brown™ Audio ADC data sheet.