SBAU413A october   2022  – may 2023

 

  1.   Abstract
  2.   Trademarks
  3. 1EVM Overview
    1. 1.1 ADS131B26Q1EVM-PDK Features
    2. 1.2 ADS131B26Q1EVM-PDK Quick-Start Guide
  4. 2Analog Interface
    1. 2.1 Terminal Blocks and Test Points
    2. 2.2 ADC1A and ADC1B
    3. 2.3 ADC2A and ADC2B
    4. 2.4 ADC3A and ADC3B
  5. 3Digital Interface
    1. 3.1 Connection to the PHI Controller
    2. 3.2 Digital Header
    3. 3.3 Clock Options
  6. 4Power Supplies
    1. 4.1 DC/DC Converter Circuit
    2. 4.2 ADC Power Supplies
    3. 4.3 Power Supply and Voltage Reference Decoupling
  7. 5ADS131B26Q1EVM-PDK Initial Setup
    1. 5.1 Default Jumper Settings
    2. 5.2 EVM Graphical User Interface (GUI) Software Installation
  8. 6ADS131B26Q1EVM-PDK Software Reference
    1. 6.1 Global Settings for ADC Control
    2. 6.2 Register Map Configuration
      1. 6.2.1 Register Map Basics
      2. 6.2.2 ADC1A, ADC3A and ADC1B, ADC3B Configuration
      3. 6.2.3 ADC2A and ADC2B Configuration
    3. 6.3 Analysis Tools
      1. 6.3.1 Time Domain Display
      2. 6.3.2 Spectral Analysis Tool
      3. 6.3.3 Histogram Analysis
      4. 6.3.4 Sequencer Analysis
  9. 7ADS131B26Q1EVM-PDK Bill of Materials, PCB Layout, and Schematics
    1. 7.1 Bill of Materials (BOM)
    2. 7.2 PCB Layout
    3. 7.3 Schematics
  10. 8Revision History

6.1 Global Settings for ADC Control

Figure 6-1 displays the default view of the ADS131B26-Q1 EVM GUI after start-up and successful connection to the EVM hardware. The EVM connection status can be verified by observing the green light indicator next to HW Connected at the bottom of the screen.

The Pages section at the top-left corner of the window lists the multiple register map controls and data analysis tools supported in this GUI. Section 6.2.1 through Section 6.2.3 detail the pages that configure the ADS131B26-Q1 register settings. Section 6.3.1 through Section 6.3.4 detail the pages that display and analyze the raw conversion data from the high-resolution, 24-bit ADC channels and the 16-bit sequencer ADC channels.

Below the Pages section is an abbreviated list of device commands, which execute the RESET, LOCK, and UNLOCK SPI op-codes. The RESET command restores the device register configuration to the power-on default settings. The LOCK command locks the interface to prevent unwanted commands from changing the state of the device. The UNLOCK command unlocks the interface to allow device configuration changes.

In the Data Capture Configuration section are basic settings and controls to initiate a data capture from the main ADC channels. OSR13A and OSR13B allow data rates to be configured for ADC1A, ADC1B, ADC3A, and ADC3B. DRDYn Driving Source selects which ADC channel generates the data-ready interrupt used for data collection. The Samples drop-down menu allows the user to choose from a pre-populated list of sample sizes or to enter a custom sample quantity. The number of samples are collected contiguously in a single data set when the Capture button is clicked from any of the analysis tool pages.

The CLK Frequency (Hz) and Data Rate (SPS) fields display the current clock frequency and ADC data rate based on the current OSR settings. If a target SCLK frequency (Hz) is specified, the GUI tries to match this frequency as closely as possible by changing the PHI PLL settings.

The GUI is switched between hardware mode and simulation mode by checking and un-checking the Connect to Hardware box in the top-right area of the screen at any time.

GUID-20220920-SS0I-99N7-WS6D-89CZ7LFKD1KT-low.svgFigure 6-1 EVM GUI Global Input Parameters