SBAU413A october   2022  – may 2023

 

  1.   Abstract
  2.   Trademarks
  3. 1EVM Overview
    1. 1.1 ADS131B26Q1EVM-PDK Features
    2. 1.2 ADS131B26Q1EVM-PDK Quick-Start Guide
  4. 2Analog Interface
    1. 2.1 Terminal Blocks and Test Points
    2. 2.2 ADC1A and ADC1B
    3. 2.3 ADC2A and ADC2B
    4. 2.4 ADC3A and ADC3B
  5. 3Digital Interface
    1. 3.1 Connection to the PHI Controller
    2. 3.2 Digital Header
    3. 3.3 Clock Options
  6. 4Power Supplies
    1. 4.1 DC/DC Converter Circuit
    2. 4.2 ADC Power Supplies
    3. 4.3 Power Supply and Voltage Reference Decoupling
  7. 5ADS131B26Q1EVM-PDK Initial Setup
    1. 5.1 Default Jumper Settings
    2. 5.2 EVM Graphical User Interface (GUI) Software Installation
  8. 6ADS131B26Q1EVM-PDK Software Reference
    1. 6.1 Global Settings for ADC Control
    2. 6.2 Register Map Configuration
      1. 6.2.1 Register Map Basics
      2. 6.2.2 ADC1A, ADC3A and ADC1B, ADC3B Configuration
      3. 6.2.3 ADC2A and ADC2B Configuration
    3. 6.3 Analysis Tools
      1. 6.3.1 Time Domain Display
      2. 6.3.2 Spectral Analysis Tool
      3. 6.3.3 Histogram Analysis
      4. 6.3.4 Sequencer Analysis
  9. 7ADS131B26Q1EVM-PDK Bill of Materials, PCB Layout, and Schematics
    1. 7.1 Bill of Materials (BOM)
    2. 7.2 PCB Layout
    3. 7.3 Schematics
  10. 8Revision History

3.2 Digital Header

In addition to the PHI connector, header J7 on the EVM is connected to the digital inputs and outputs between the ADS131B26-Q1 and the PHI connector. Each row is shorted across both pins to allow access to an external logic analyzer or oscilloscope and an external controller simultaneously. Table 3-2 lists the digital header pins.

Table 3-2 DEBUG Header Pins (J7)
Signal NameDigital Header Pins
GPIO0/MHDJ7[1-2]
CSnJ7[3-4]
SDIJ7[5-6]
SDOJ7[7-8]
SCLKJ7[9-10]
DRDYnJ7[11-12]
GPIO1J7[13-14]
GPIO2/FAULTJ7[15-16]
GPIO3/OCCAJ7[17-18]
RESETnJ7[19-20]
GPIO4/OCCBJ7[21-22]
DGNDJ7[23-24]