SBAU467C October   2024  – August 2026

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Required Hardware
    2. 2.2 Required Software
  8. 3Quick Start Guide
    1. 3.1 Introduction
    2. 3.2 Hardware Setup
    3. 3.3 Software Setup
      1. 3.3.1 ADC32RF5xEVM GUI Installation
      2. 3.3.2 High Speed Data Converter Pro GUI Installation
    4. 3.4 Quick Start Procedure for Bypass Mode
      1. 3.4.1 2x Averaging in Bypass Mode
    5. 3.5 Quick Start Procedure for Complex Decimation Mode
      1. 3.5.1 8x Complex Decimation
      2. 3.5.2 128x Complex Decimation
    6. 3.6 Operating Modes
      1. 3.6.1 Analog Input Configuration
      2. 3.6.2 Quad ADC Mode
  9. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials (BOM)
  10. 5Additional Information
    1. 5.1 Trademarks
  11. 6Related Documentation
  12. 7Revision History

Features

  • An input channel featuring TI's fully-differential RF amplifier TRF1305 allowing a single-ended signal input with bandwidth from dc-2GHz.
  • An input channel featuring dual TRF1305 devices in a noise reduction scheme.
  • LMK04832 system clock generator that generates field-programmable gate array (FPGA) reference clocks for the high-speed serial interface.
  • Flexible common-mode interface and dc coupling enabled by the TRF1305.