SBOS109B September 1999 – December 2025 INA146
PRODUCTION DATA
at TA = 25°C, VS = ±15V, G = 0.1, RL = 10kΩ connected to ground, VREF = VS / 2, all chips site origins (CSO), unless otherwise noted
Figure 5-1 Offset Voltage Production Distribution
Figure 5-3 Offset Voltage Drift Production Distribution
| CSO: SHE |

| CSO: SHE |
Figure 5-9 Input Voltage Noise Density
| CSO: SHE |

| CSO: SHE |
Figure 5-15 Gain and Phase vs Frequency Op Amp A1 and A2
| CSO: SHE |
| CSO: TID |
Figure 5-21 Small-signal Step Response (G = 0.1, CL = 1000pF)
| CSO: SHE |
Figure 5-2 Offset Voltage Production Distribution
| CSO: TID |
| CSO: TID |
| CSO: TID |
| CSO: TID |
Figure 5-16 Settling Time vs Load Capacitance| CSO: TID |

Figure 5-22 Small-signal Step Response (G = 1, CL = 1000pF)| CSO: TID |