SBOS109B September   1999  – December 2025 INA146

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Amplifier A1, A2 Performance
    7. 5.7 Typical Characteristics
  7. 6 Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Operating Voltage
      2. 6.1.2 Setting the Gain
      3. 6.1.3 Common-mode Range
      4. 6.1.4 Offset Trim
      5. 6.1.5 Input Impedance
  8. 7 Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Device Nomenclature
    2. 7.2 Third-Party Products Disclaimer
    3. 7.3 Documentation Support
      1. 7.3.1 Related Documentation
    4. 7.4 Receiving Notification of Documentation Updates
    5. 7.5 Support Resources
    6. 7.6 Trademarks
    7. 7.7 Electrostatic Discharge Caution
    8. 7.8 Glossary
  9. 8 Revision History
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

at TA = 25°C, VS = ±2.25V to ±18V or 5V single supply, RL = 10kΩ, VREF = VS / 2, VCM = VS / 2, and G = 0.1, all chips site origins (CSO), unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
VOS Offset voltage, VO RTI, VS = ±15V, VCM = 0V ±1 ±5 mV
RTI, VS = 5V, VCM = 0V ±3 ±10
Offset voltage, VO1 RTI ±1
Offset voltage drift  RTI, TA = –40℃ to 85℃ ±10 µV/°C
PSRR Power-supply rejection ratio  RTI, VS = ±1.35V to ±18V ±100 ±600 µV/V
VCM Common-mode voltage (1) VS = ±15V, VIN = 0V –100 100 V
VS = 5V, VIN = 0V –25 19
CMRR Common-mode voltage rejection RTI,  VCM = [11(VS–)–10*VREF] to [11*(VS+ -1)–10*VREF] , RS = 0Ω  70 80 dB
TA = –40℃ to 85℃ 64 74
Differential input impedance Non-inverting input 110 kΩ
Inverting input 91.7
Common-mode input impedance 55 kΩ
BIAS CURRENT
IB Bias Current VCM = VS / 2 ±50 nA
IOS Offset Current ±5 nA
NOISE
eN Voltage noise RTI, fB = 0.1Hz to 10Hz 12 µVPP 
RTI, f = 1kHz 550 nV/√Hz
GAIN
Gain  0.1 100 V/V
GE Gain error VO = (VS–) + 0.15V to (VS+) – 1V, RL = 100kΩ, G = 1 ±0.025 ±0.1 %
VO = (VS–) + 0.3V to (VS+) – 1.25V, RL = 10kΩ, G = 1 ±0.025 ±0.1
Gain error drift(2) TA = –40°C to 85°C  VO = (VS–) + 0.25V to (VS+) – 1V, RL = 100kΩ, G = 1 ±1 ±10 ppm/°C
VO = (VS–) + 0.5V to (VS+) – 1.25V, RL = 10kΩ, G = 1 ±1 ±10
Gain nonlinearity VO = (VS–) + 0.3V to (VS+) – 1.25V, G = 1 ±0.001 ±0.01 % of FSR
OUTPUT
Output voltage RL = 100kΩ, G = 1 (VS–) + 0.15 (VS+) – 1 V
TA = –40℃ to 85℃  (VS–) + 0.25 (VS+) – 1
RL = 10kΩ, G = 1 (VS–) + 0.3 (VS+) – 1.25
TA = –40℃ to 85℃ (VS–) + 0.5 (VS+) – 1.25
CL Load capacitance Stable operation 1 nF
ISC Short-circuit current Continuous to VS / 2 CSO: SHE ±15 mA
CSO: TID ±27
FREQUENCY RESPONSE
BW Bandwidth, –3dB G = 0.1 550 kHz
G = 1 50
SR Slew rate CSO: SHE 0.45 V/µs
CSO: TID 0.3
tS Settling time To 0.1% VO = 10V-step 40 µs
To 0.01% VO = 10V-step 80
Overload recovery 50% input overload CSO: SHE 40 µs
CSO: TID 2
POWER SUPPLY
IQ Quiescent current VIN = 0V CSO: SHE ±570 ±700 µA
CSO: TID ±250 ±700 µA
TA = –40℃ to 85℃ ±750 µA
(1) Input common-mode voltage varies with output voltage; see Typical Characteristics.
(2) Specified by wafer test.