SBOS847B July   2022  – December 2024 OPA817

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics: VS = ±5 V
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input and ESD Protection
      2. 7.3.2 Feedback Pin
      3. 7.3.3 FET-Input Architecture With Wide Gain-Bandwidth Product
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Down (PD) Pin
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Wideband, High-Input-Impedance DAQ Front End
    2. 8.2 Typical Applications
      1. 8.2.1 High-Input-Impedance, 200-MHz, Digitizer Front-End Amplifier Design
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Considerations
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.4.1.1 Thermal Considerations

The OPA817 does not require a heat sink or airflow in most applications. The maximum allowed junction temperature sets the maximum allowed internal power dissipation as described in the following paragraph. Do not allow the maximum junction temperature to exceed 150°C.

Operating junction temperature (TJ) is given by TA + PD × RθJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is the specified no-load supply current times the total supply voltage across the part. PDL depends on the required output signal and load, but for a grounded resistive load, PDL is at a maximum when the output is fixed at a voltage equal to 1/2 of either supply voltage (for balanced bipolar supplies). Under this condition PDL = VS2 / (4 × RL) where RL includes feedback network loading.

The power in the output stage and not into the load determines internal power dissipation.

As a worst-case example, compute the maximum TJ using the OPA817 in the circuit of Figure 8-1 operating at the maximum specified ambient temperature of +105°C and driving a grounded 100-Ω load.

PD = 10 V × 23.5 mA + 52 / (4 × (100 Ω || 500 Ω)) ≅ 310 mW

Maximum TJ = 105°C + (0.310 W × 64.9°C/W) = 125.1°C.

All actual applications operate at lower internal power and junction temperature.