SBOS957F February   2022  – October 2025 OPA2328 , OPA328 , OPA4328

PRODMIX  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information - OPA328
    5. 5.5 Thermal Information - OPA2328
    6. 5.6 Thermal Information - OPA4328
    7. 5.7 Electrical Characteristics
    8. 5.8 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input and ESD Protection
      2. 6.3.2 Rail-to-Rail Input
      3. 6.3.3 Phase Reversal
    4. 6.4 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Capacitive Load and Stability
    2. 7.2 Typical Applications
      1. 7.2.1 Bidirectional Current-Sensing
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Transimpedance Amplifier
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 PSpice® for TI
        2. 8.1.1.2 TINA-TI™ Simulation Software (Free Download)
        3. 8.1.1.3 DIP-Adapter-EVM
        4. 8.1.1.4 DIYAMP-EVM
        5. 8.1.1.5 Analog Filter Designer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Pin Configuration and Functions

OPA328 OPA2328 OPA4328 OPA328 DBV Package5-Pin SOT-23(Top
                        View)Figure 4-1 OPA328 DBV Package
5-Pin SOT-23
(Top View)
OPA328 OPA2328 OPA4328 OPA328S DBV Package
                            (Preview)6-Pin SOT-23(Top View)Figure 4-2 OPA328S DBV Package (Preview)
6-Pin SOT-23
(Top View)
Pin Functions: OPA328 and OPA328S
PIN TYPE DESCRIPTION
NAME OPA328 OPA328S
–IN 4 4 Input Negative (inverting) input
+IN 3 3 Input Positive (noninverting) input
OUT, VOUT 1 1 Output Output
SHDN 5 Input Shutdown, active low
V– 2 2 Power Negative (lowest) power supply
V+ 5 6 Power Positive (highest) power supply
OPA328 OPA2328 OPA4328 OPA2328 D and DGK
                            Package8-pin SOIC and and VSSOP(Top View)Figure 4-3 OPA2328 D and DGK Package
8-pin SOIC and and VSSOP
(Top View)
OPA328 OPA2328 OPA4328 OPA2328 YBJ Package24-Pin DSBGA(Top View)Figure 4-5 OPA2328 YBJ Package
24-Pin DSBGA
(Top View)
OPA328 OPA2328 OPA4328 OPA2328 DRG Package, 8-Pin WSON(Top
                        View)Figure 4-4 OPA2328 DRG Package,
8-Pin WSON
(Top View)
Pin Functions: OPA2328
PIN TYPE DESCRIPTION
NAME D (SOIC), DGK (VSSOP), DRG (WSON) YBJ (DSBGA)
–IN A 2 A1 Input Inverting input, channel A
+IN A 3 A3 Input Noninverting input, channel A
–IN B 6 E1 Input Inverting input, channel B
+IN B 5 E3 Input Noninverting input, channel B
OUT A 1 A2 Output Output, channel A
OUT B 7 E2 Output Output, channel B
SHDN D5 Input Shutdown control for both channel A and channel B. Logic level low = amplifiers enabled. Logic level high = amplifiers disabled.
V– 4 C5, E5 Power Negative (lowest) power supply
V+ 8 A4, A5, B5, E4 Power Positive (highest) power supply
DNC B1, B2, B3, B4, C1, C2, C4, D1, D2, D3, D4 Do not connect
OPA328 OPA2328 OPA4328 OPA4328 PW Package14-Pin TSSOP(Top
                    View) Figure 4-6 OPA4328 PW Package
14-Pin TSSOP
(Top View)
Table 4-1 Pin Functions: OPA4328
PIN TYPE DESCRIPTION
NAME NO.
PW (TSSOP)
–IN A 2 Input Inverting input, channel A
+IN A 3 Input Noninverting input, channel A
–IN B 6 Input Inverting input, channel B
+IN B 5 Input Noninverting input, channel B
–IN C 9 Input Inverting input, channel C
+IN C 10 Input Noninverting input, channel C
–IN D 13 Input Inverting input, channel D
+IN D 12 Input Noninverting input, channel D
OUT A 1 Output Output, channel A
OUT B 7 Output Output, channel B
OUT C 8 Output Output, channel C
OUT D 14 Output Output, channel D
V– 11 Power Negative (lowest) power supply
V+ 4 Power Positive (highest) power supply