SBOSA23H May   2020  – October 2026 TLV9151-Q1 , TLV9152-Q1 , TLV9154-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information for Single Channel
    5. 5.5 Thermal Information for Dual Channel
    6. 5.6 Thermal Information for Quad Channel
    7. 5.7 Electrical Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 EMI Rejection
      2. 6.3.2 Thermal Protection
      3. 6.3.3 Capacitive Load and Stability
      4. 6.3.4 Common-Mode Voltage Range
      5. 6.3.5 Phase Reversal Protection
      6. 6.3.6 Electrical Overstress
      7. 6.3.7 Overload Recovery
      8. 6.3.8 Typical Specifications and Distributions
      9. 6.3.9 Shutdown
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Low-Side Current Measurement
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 TINA-TI (Free Software Download)
        2. 8.1.1.2 TI Precision Designs
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.3.9 Shutdown

The TLV915xS-Q1 devices feature one or more shutdown pins (SHDN) that disable the op amp, placing the amplifier into a low-power standby mode. In this mode, the op amp typically consumes about 30µA. The SHDN pins are active high, meaning that shutdown mode enables when the input to the SHDN pin is a valid logic high.

The SHDN pins are referenced to the negative supply rail of the op amp. The threshold of the shutdown feature lies around 800mV (typical) and does not change with respect to the supply voltage. Hysteresis is included in the switching threshold to provide smooth switching characteristics. For proper shutdown behavior, drive the SHDN pins with valid logic signals. The definition of a valid logic low is a voltage from V– and V– + 0.2V. The definition of a valid logic high is a voltage from V– + 1.1V and V+. The shutdown pin circuitry includes a pulldown resistor, which inherently pulls the voltage of the pin to the negative supply rail if not driven. Thus, to enable the amplifier, the SHDN pins must either be left floating or driven to a valid logic low. To disable the amplifier, the SHDN pins must be driven to a valid logic high. The maximum voltage allowed at the SHDN pins is V+. Exceeding this voltage level can damage the device.

The SHDN pins are high-impedance CMOS inputs. Channels of single and dual op amp packages are independently controlled, and channels of quad op amp packages are controlled in pairs. For battery-operated applications, use this feature to greatly reduce the average current and extend battery life. The typical enable time out of shutdown is 8µs; disable time is 3µs. When disabled, the output assumes a high-impedance state. This architecture allows the TLV915xS-Q1 family to operate as a gated amplifier, multiplexer, or programmable-gain amplifier. Shutdown time (tOFF) depends on loading conditions and increases as load resistance increases. To keep shutdown (disable) within a specific shutdown time, the specified 10kΩ load to midsupply (VS / 2) is required. If using the TLV915xS-Q1 without a load, the resulting turnoff time significantly increases.