SBOSA33C September   2021  – June 2026 LMH5485-SP

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Related Products
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics for VS = 5V
    6. 6.6  Electrical Characteristics for VS = 3V
    7. 6.7  Quality Conformance Inspection
    8. 6.8  Typical Characteristics: 5V Single Supply
    9. 6.9  Typical Characteristics: 3V Single Supply
    10. 6.10 Typical Characteristics: 3V to 5V Supply Range
  8. Parameter Measurement Information
    1. 7.1 Example Characterization Circuits
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Differential I/O
      2. 8.3.2 Power-Down Control Pin (PD)
        1. 8.3.2.1 Operating the Power Shutdown Feature
      3. 8.3.3 Input Overdrive Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation from Single-Ended Sources to Differential Outputs
        1. 8.4.1.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversion
        2. 8.4.1.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversion
      2. 8.4.2 Differential-Input to Differential-Output Operation
        1. 8.4.2.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
        2. 8.4.2.2 DC-Coupled, Differential-Input to Differential-Output Design Issues
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Interfacing to High-Performance ADCs
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Detailed Design Procedure

The LMH5485-SP provides a simple interface to a wide variety of precision SAR, ΔΣ, or higher-speed pipeline ADCs. To deliver the exceptional distortion at the output pins, considerably wider bandwidth than typically required in the signal path to the ADC inputs is provided by the LMH5485-SP. For instance, the gain-of-2, single-ended-to-differential design example provides approximately a 500MHz, small-signal bandwidth. Even if the source signal is Nyquist bandlimited, this broad bandwidth can possibly integrate enough LMH5485-SP noise to degrade the SNR through the ADC if the broadband noise is not bandlimited between the amplifier and ADC. Figure 9-1 shows an example dc-coupled, gain-of-2 interface with a controlled, interstage-bandwidth filter.

Designed for a DC-coupled 50Ω input match, this design starts with a 499Ω feedback resistor, and provides a gain of 2.35V/V to the LMH5485-SP output pins. The third-order interstage, low-pass filter provides a 20MHz Bessel response with a 0.85V/V insertion loss to the ADC, providing a net gain of 2V/V from board edge to the ADC inputs. Although the LMH5485-SP can absorb overdrives, an external protection element is added using the BAV99 low-capacitance device (see also Figure 9-1). For dc-coupled testing, pins 1 and 2 of JP1 are jumpered together. When the source is an ac-coupled, 50Ω source, pins 2 and 3 of JP1 are jumpered to maintain differential balance.