SBOSA95G May   2022  – December 2024 OPA2863A , OPA863A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information OPA863A
    5. 6.5  Thermal Information OPA2863A
    6. 6.6  Electrical Characteristics VS = ±5 V
    7. 6.7  Electrical Characteristics VS = 3 V
    8. 6.8  Typical Characteristics: VS = ±5 V
    9. 6.9  Typical Characteristics: VS = 3 V
    10. 6.10 Typical Characteristics: VS = 3 V to 10 V
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Stage
      2. 7.3.2 Output Stage
        1. 7.3.2.1 Overload Power Limit
      3. 7.3.3 ESD Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Down Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Active Filters
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Low-Power SAR ADC Driver and Reference Buffer
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.6 Electrical Characteristics VS = ±5 V

at G = 1 V/V, RF = 0 Ω for G = 1 V/V, otherwise RF = 1 kΩ for other gains, CL = 1 pF, RL = 2 kΩ referenced to mid-supply, input and output common-mode is at mid-supply, and TA ≅ 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
SSBW Small-signal bandwidth VOUT = 20 mVPP, G = 1 105 MHz
GBWP Gain-bandwidth product 50 MHz
LSBW Large-signal bandwidth VOUT = 2 VPP 14 MHz
Bandwidth for 0.1-dB flatness VOUT = 20 mVPP 15 MHz
SR Slew rate VOUT = 2-V step 100 V/µs
Rise, fall time VOUT = 200-mV step 9 ns
Settling time To 0.1%, VOUT = 2-V step 50 ns
To 0.01%, VOUT = 2-V step 70
Overshoot and undershoot VOUT = 2-V step 1 %
Overdrive recovery time G = –1, 0.5-V overdrive beyond supplies 70 ns
G = 1, 0.5-V overdrive beyond supplies 90
HD2 Second-order harmonic distortion f = 20 kHz, VOUT = 2 VPP –129 dBc
HD3 Third-order harmonic distortion f = 20 kHz, VOUT = 2 VPP –138 dBc
HD2 Second-order harmonic distortion f = 100 kHz, VOUT = 2 VPP –107 dBc
HD3 Third-order harmonic distortion f = 100 kHz, VOUT = 2 VPP –125 dBc
eN Input voltage noise 6.3 nV/√Hz
iN Input current noise 0.5 pA/√Hz
Closed-loop output impedance f = 1 MHz 0.2 Ω
Channel-to-channel crosstalk f = 1 MHz, VOUT = 2 VPP –120 dBc
DC PERFORMANCE
AOL Open-loop voltage gain VOUT = ±2.5 V 110 128 dB
VOS Input-referred offset voltage –95 ±10 95 µV
Input offset voltage drift TA = –40°C to +125°C –1.2 ±0.3 1.2 µV/°C
Input bias current  TA ≅ 25°C 0.3 0.73 µA
TA = –40°C to +85°C 1.2
TA = –40°C to +125°C 1.6
Input bias current drift TA = –40°C to +125°C ±3 nA/°C
Input offset current –30 ±10 30 nA
INPUT
Input common-mode voltage VS––0.2 VS++0.2 V
CMRR Common-mode rejection ratio VCM = VS– – 0.2 V to VS+ – 1.6 V 95 120 dB
Input impedance common-mode 650 || 0.8 MΩ || pF
Input impedance differential mode 200 || 0.5 kΩ || pF
OUTPUT
VOL Output voltage, low TA ≅ 25°C VS–+0.14 VS–+0.2 V
TA = –40°C to +125°C VS–+0.15 VS–+0.22
VOH Output voltage, high TA ≅ 25°C VS+–0.2 VS+–0.14 V
TA = –40°C to +125°C VS+–0.2 VS+–0.15
Linear output drive
(sourcing and sinking)		 VOUT = ±2.5 V, ΔVOS < 1 mV(1) 23 30 mA
Short-circuit current 45 mA
POWER SUPPLY
IQ Quiescent current per amplifier TA ≈ 25°C 800 925 µA
TA = –40°C to +125°C 1040
PSRR Power-supply rejection ratio ΔVS = ±2 V(2) 100 120 dB
POWER DOWN
Enable voltage threshold Specified on when > VS+ – 0.5 V 4.5 V
Disable voltage threshold Specified off when < VS+ – 1.5 V 3.5 V
Power-down quiescent current per channel VPD ≤ VS+ – 1.5 V 11 28 µA
VPD ≤ VS+ – 1.5 V, TA = –40°C to +125°C 35
Power-down pin bias current 1 2.5 µA
Turn-on time delay 8 µs
Turn-off time delay 3.5 µs
AUXILIARY INPUT STAGE
Gain-bandwidth product 50 MHz
Input voltage noise 6.3 nV/√Hz
Input current noise 0.5 pA/√Hz
Input-referred offset voltage –95 ±10 95 μV
Input bias current TA ≅ 25°C 0.2 0.6 µA
TA = –40°C to +125°C 0.2 1.3
Common-mode rejection ratio VCM = 4.1 V to 5.2 V 120 dB
Power supply rejection ratio ΔVS = ±0.6 V 120 dB
(1) Change in input offset voltage from no-load condition.
(2)
Change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to
+PSRR and –PSRR.