SBOSAK6 June   2025 THS4535

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics for External Gain
    6. 6.6 Electrical Characteristics for Internal Gain
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Common-Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Down Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Output Common-Mode Voltage
        1. 8.1.1.1 Resistor Matching
      2. 8.1.2 Data Converters
      3. 8.1.3 Single-Supply Applications
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Board Layout Recommendations
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

THS4535 DGK Package, 8-Pin VSSOP (Top View), External GainFigure 5-1 DGK Package, 8-Pin VSSOP (Top View), External Gain
THS4535 RUN Package, 10-Pin WQFN (Top View), External GainFigure 5-2 RUN Package, 10-Pin WQFN (Top View), External Gain
THS4535 DGK Package, 8-Pin VSSOP (Top View), Internal GainFigure 5-3 DGK Package, 8-Pin VSSOP (Top View), Internal Gain
THS4535 RUN Package, 10-Pin WQFN (Top View), Internal GainFigure 5-4 RUN Package, 10-Pin WQFN (Top View), Internal Gain
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
DGK (VSSOP) RUN (WQFN)
FDA_IN– — 2 Input Inverting (negative) amplifier input (internal gain)
FDA_IN+ — 8 Input Noninverting (positive) amplifier input (internal gain)
IN– 1 6 Input Inverting (negative) amplifier input
IN+ 8 4 Input Noninverting (positive) amplifier input
NC — 2, 8 — Leave unconnected (external gain)
OUT– 5 1 Output Inverting (negative) amplifier output
OUT+ 4 9 Output Noninverting (positive) amplifier output
PD 7 3 Input Power down. PD = logic low = power off mode; PD = logic high = normal operation.
VOCM 2 7 Input Output common-mode voltage control input
VS– 6 5 Power Negative power-supply input
VS+ 3 10 Power Positive power-supply input