SBOSAK6A June   2025  – December 2025 THS4535

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Common-Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Down Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Output Common-Mode Voltage
        1. 8.1.1.1 Resistor Matching
      2. 8.1.2 Data Converters
      3. 8.1.3 Single-Supply Applications
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Board Layout Recommendations
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

at TA = 25°C, VS+ – VS− = 5V, VOCM(1) = open, RF = 1kΩ, differential gain (G) = 1V/V, VO = 2VPP, RL = 1kΩ, and PD = logic high (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE 
SSBW Small-signal bandwidth VO = 100mVPP G = 1V/V,
< 1dB peaking		 65 MHz
G = 2V/V 42
G = 5V/V 16
G = 10V/V 9
GBWP Gain-bandwidth product VO = 100mVPP, G = 20V/V 80 MHz
LSBW Large-signal bandwidth VO = 2VPP, G = 1V/V 17 MHz
Bandwidth for 0.1dB flatness VO = 2VPP, G = 1V/V 8 MHz
SR Slew rate (20%–80%) VO = 2V step Rising 47 V/µs
Falling 57
Overshoot and undershoot VO = 2V step, 8ns input rise time 5 %
tS Settling time VO = 2V step To 0.1% 100 ns
To 0.01% 150
Rise and fall time (10%–90%) VO = 2V step, 8ns input rise time 30 ns
HD2 Second-order harmonic distortion VO = 2VPP f = 1kHz 140 dBc
f = 10kHz 125
f = 1MHz 85
VO = 8VPP f = 1kHz 135
f = 10kHz 125
f = 1MHz 60
HD3 Third-order harmonic distortion VO = 2VPP f = 1kHz 135 dBc
f = 10kHz 114
f = 1MHz 74
VO = 8VPP f = 1kHz 126
f = 10kHz 106
f = 1MHz 58
en Input differential voltage noise f = 100kHz 4.3 nV/√Hz
1/f corner 2.4 kHz
in Input current noise f = 100kHz 70 fA/√Hz
Overdrive recovery time G = 2V/V 750 ns
ZOUT Closed-loop output impedance f = 100kHz (differential) 0.3 Ω
DC PERFORMANCE
AOL Open-loop voltage gain VO = ±2V 100 126 dB
AOL Open-loop voltage gain VO = ±2.3V, RL = 40Ω 100 126 dB
VOS Input offset voltage ±0.5 ±1.4 mV
Input offset voltage drift TA = –40°C to +125°C ±0.3 ±1.4 µV/°C
IB+, IB– Input bias current(3) TA = 25°C ±0.2 ±20 pA
TA = –40°C to +125°C ±20 ±40
IOS Input offset current(4) TA = 25°C ±0.2 ±20 pA
TA = –40°C to +125°C ±0.2 ±30
INPUT
VICML Common-mode voltage
input low		 TA = 25°C VS– – 0.3 VS– – 0.2 V
TA = –40°C to +125°C VS– – 0.2 VS– – 0.1
VICMH Common-mode voltage
input high		 TA = 25°C VS+ – 1.4 VS+ – 1.3 V
TA = –40°C to +125°C VS+ – 1.5 VS+ – 1.4
CMRR Common-mode rejection ratio (VS–) < VCM < (VS+ – 1.5V), TA = 25°C 100 114 dB
Differential input impedance 15 || 3.4 TΩ || pF
Common mode input impedance 30 || 1.2 TΩ || pF
OUTPUT
Output voltage low TA = 25°C VS– + 0.1 VS– + 0.2 V
TA = –40°C to +125°C VS– + 0.1 VS– + 0.2
Output voltage high TA = 25°C VS+ – 0.2 VS+ – 0.1 V
TA = –40°C to +125°C VS+ – 0.2 VS+ – 0.1
Continuous output current (slam) VO = ±2.5V, RL = 40Ω ±90 mA
VO = ±2.5V, RL = 40Ω, TA = –40°C to +125°C  ±80
Linear output current VO = ±2.3V,
RL = 40Ω,
AOL > 100dB		 TA = 25°C ±50 ±60 mA
TA = –40°C to +125°C ±60
OUTPUT COMMON-MODE VOLTAGE (VOCM) CONTROL
VOCM(1) small-signal bandwidth VVOCM = 100mVPP 43 MHz
VOCM large-signal bandwidth VVOCM = 1VPP 16 MHz
VOCM slew rate(2) (20%–80%) VVOCM = 1V step 28 V/µs
VOCM voltage noise f = 100kHz VVOCM = midsupply (driven) 18 nV/√Hz
VOCM = open 36
DC output balance VVOCM = midsupply (driven), VO = ±1V 80 dB
AC output balance VVOCM = midsupply (driven), VOCM/VO (–3dB from dc) 50000 Hz
Gain error (VS– + 0.45) < VVOCM < (VS+ – 1.2V) 0.997 1 1.003 V/V
VOCM input bias current –5 0.3 5 µA
PSRR to VOCM 82 dB
VOCM input impedance 250 || 2.8 kΩ || pF
VOCM offset voltage VOCM pin floating –10 10 mV
VOCM offset voltage VVOCM = midsupply (driven) –5 0.25 5 mV
VOCM offset voltage drift VOCM pin floating, TA = –40°C to +125℃ –10 2 10 µV/℃
VOCM offset voltage drift VVOCM = midsupply (driven), TA = –40°C to +125℃ –10 3 10 µV/℃
VOCM voltage low < ±11mV shift from
midsupply offset, TA = 25°C		 VS– + 0.3 VS– + 0.45 V
< ±11mV shift from
midsupply offset, TA = –40°C to +125°C		 VS– + 0.5
VOCM voltage high TA = 25°C,
< ±11mV shift from midsupply offset		 VS+ – 1.2 VS+ – 1 V
TA = –40°C to +125°C,
< ±11mV shift from midsupply offset		 VS+ – 1.3
POWER SUPPLY
IQ Quiescent current VS = 5V, PD = logic high (active) TA = 25°C 4.7 5.4 mA
TA = –40°C to +125°C 4.7 5.4
IQ Quiescent current VS = 5V, PD = logic low (shutdown) TA = –40°C to +125°C 20 µA
PSRR Power-supply rejection ratio Either supply to input VOS 90 110 dB
POWER DOWN
Enable voltage threshold PD = logic high (active) VS+ – 0.5 V
Disable voltage threshold PD = logic low (shutdown) VS- + 0.5 V
Enable pin bias current PD = high 0 6 µA
PD = low –15 –10
Turn-on time delay Time from PD = high to VO = 90% of final value 5 us
Turn-off time delay Time from PD = low to VO = 10% of original value 40 ns
(1) VVOCM refers to the voltage at VOCM pin. VOCM = [(VOUT+ + VOUT–) / 2] refers to the average output voltage.
(2) Average of the rising and falling slew rate.
(3) Current out of the node is considered positive.
(4) IOS = IB+ – IB–.