SBOSAK7C December   2024  – November 2025 OPA2383 , OPA383 , OPA4383

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information OPA383
    5. 5.5 Thermal Information OPA2383
    6. 5.6 Thermal Information OPA4383
    7. 5.7 Electrical Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Bias Current
      2. 6.3.2 EMI Susceptibility and Input Filtering
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Zero-Drift Clocking
    2. 7.2 Typical Applications
      1. 7.2.1 Bidirectional Current Sensing
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Bridge Sensor Measurement
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 PSpice® for TI
        2. 8.1.1.2 TINA-TI™ Simulation Software (Free Download)
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.7 Electrical Characteristics

at TA = 25°C, RL = 10kΩ connected to VS / 2, VS = 1.7V to 5.5V, VCM = VS / 2, VOUT = VS / 2, and min and max specification established from manufacturing final test (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage(1)  VS = 5.5V ±0.4 ±5 µV
TA = –40°C to +125°C ±0.5
dVOS/dT Input offset voltage drift TA = –40°C to +125°C(1) ±0.004 ±0.025 μV/°C
PSRR Power supply rejection ratio ±0.05 ±0.9 μV/V
TA = –40°C to +125°C(1) ±0.9
INPUT BIAS CURRENT
IB Input bias current(1) ±10 ±62 pA
TA = –40°C to +85°C ±76
TA = –40°C to +125°C ±212
IOS Input offset current(1) ±20 ±123 pA
TA = –40°C to +125°C ±300
NOISE
  Input voltage noise f = 0.1Hz to 10Hz   650   nVPP
  100   nVRMS
eN Input voltage noise density f = 1Hz   32   nV/√Hz
f = 10Hz   32  
f = 100Hz   32  
f = 1kHz   32  
iN Input current noise f = 1kHz   100   fA/√Hz
VCM Common-mode voltage range VS = 5.5V (V–) – 0.1 (V+) + 0.1 V
VS = 1.7V (V–) – 0.1 (V+)
INPUT VOLTAGE
CMRR Common-mode rejection ratio (V–) – 0.1V < VCM < (V+) + 0.1V, VS = 5.5V 122 135 dB
TA = –40°C to +125°C(1) 120
(V–) – 0.1V < VCM < (V+), VS = 1.7V(1) 116 130
TA = –40°C to +125°C 114
INPUT CAPACITANCE
ZID Differential 100 || 6 MΩ || pF
ZICM Common-mode 60 || 1.5 GΩ || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain (V–) + 100mV < VOUT <
(V+) – 100mV		 VS = 5.5V 120 145 dB
VS = 1.7V(1) 120
TA = –40°C to +125°C(1) 119
(V–) + 150mV < VOUT <
(V+) – 150mV,
RL = 2kΩ		 VS = 5.5V 119 140
VS = 1.7V(1) 119
TA = –40°C to +125°C(1) 118
FREQUENCY RESPONSE
GBW Gain-bandwidth product 2.5 MHz
SR Slew rate 4V step, G = +1 1 V/μs
tS Settling time To 0.1%, 1V step, G = +1 5.4 μs
To 0.01%, 1V step, G = +1 48
Overload recovery time VIN  × G > VS 2200 ns
Chopping clock frequency(1) 130 kHz
THD+N Total harmonic distortion + noise VOUT = 1VRMS, G = +1, f = 1kHz 0.0012 %
OUTPUT
Voltage output swing from rail No load 1 10 mV
5 30
RL = 2kΩ 60 150
TA = –40°C to +125°C(1) 155
High linearity output swing range(1) AOL > 119dB (V–) + 0.075 (V+) – 0.075 V
RL = 2kΩ (V–) + 0.150 (V+) – 0.150
ISC Short-circuit current VS = 5.5V ±28 mA
VS = 1.7V ±2.5
CLOAD Capacitive load drive See the typical characteristic curve
RO Open-loop output impedance f = 1MHz 2.5 kΩ
POWER SUPPLY
IQ Quiescent current per amplifier IO = 0mA 65 100 μA
TA = –40°C to 125°C(1) 110
Turn-on time At VS = 5.5V, VS ramp rate > 0.05V/µs, settle to 1% 180 μs
(1) Specification established from device population bench system measurements across multiple lots.