SBOSAM4A December   2024  – June 2026 TLV9141 , TLV9142 , TLV9144

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information for Single Channel
    5. 5.5 Thermal Information for Dual Channel
    6. 5.6 Thermal Information for Quad Channel
    7. 5.7 Electrical Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Protection Circuitry
      2. 6.3.2 Common-Mode Voltage Range
      3. 6.3.3 EMI Rejection
      4. 6.3.4 Phase Reversal Protection
      5. 6.3.5 Electrical Overstress
      6. 6.3.6 Overload Recovery
      7. 6.3.7 Typical Specifications and Distributions
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Low-Side Current Measurement
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 TINA-TI (Free Software Download)
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

TLV9141 TLV9142 TLV9144 TLV9141 D Package8-Pin SOIC(Top View)
NC- no internal connection
Figure 4-1 TLV9141 D Package
8-Pin SOIC
(Top View)
TLV9141 TLV9142 TLV9144 TLV9141 DCK Package5-Pin SC70(Top View)Figure 4-3 TLV9141 DCK Package
5-Pin SC70
(Top View)
TLV9141 TLV9142 TLV9144 TLV9141 DBV Package5-Pin SOT-23(Top View)Figure 4-2 TLV9141 DBV Package
5-Pin SOT-23
(Top View)
Table 4-1 Pin Functions: TLV9141
PIN TYPE(1) DESCRIPTION
NAME D DBV DCK
IN– 2 4 3 I Inverting input
IN+ 3 3 1 I Noninverting input
NC 1, 5, 8 — — — Do not connect
OUT 6 1 4 O Output
V– 4 2 2 — Negative (lowest) power supply
V+ 7 5 5 — Positive (highest) power supply
(1) I = input, O = output
TLV9141 TLV9142 TLV9144 TLV9142 D, DDF, DGK, PW, and N Package,8-Pin SOIC, TSSOP, and PDIP (Top View)Figure 4-4 TLV9142 D, DDF, DGK, PW, and N Package,
8-Pin SOIC, TSSOP, and PDIP
(Top View)
NC- no internal connection
Figure 4-5 TLV9142 RUG Package,
10-Pin X2QFN
(Top View)
Table 4-2 Pin Functions: TLV9142
PIN TYPE(1) DESCRIPTION
NAME D, DDF, DGK, PW, N RUG
IN1+ 3 10 I Noninverting input, channel 1
IN1– 2 9 I Inverting input, channel 1
IN2+ 5 4 I Noninverting input, channel 2
IN2– 6 5 I Inverting input, channel 2
NC — 2, 3 — Do not connect
OUT1 1 8 O Output, channel 1
OUT2 7 6 O Output, channel 2
V+ 8 7 — Positive (highest) power supply
V– 4 1 — Negative (lowest) power supply
(1) I = input, O = output
TLV9141 TLV9142 TLV9144 TLV9144 D and PW Package14-Pin SOIC and TSSOP(Top View)Figure 4-6 TLV9144 D and PW Package
14-Pin SOIC and TSSOP
(Top View)
Table 4-3 Pin Functions: TLV9144
PIN TYPE(1) DESCRIPTION
NAME NO.
IN1+ 3 I Noninverting input, channel 1
IN1– 2 I Inverting input, channel 1
IN2+ 5 I Noninverting input, channel 2
IN2– 6 I Inverting input, channel 2
IN3+ 10 I Noninverting input, channel 3
IN3– 9 I Inverting input, channel 3
IN4+ 12 I Noninverting input, channel 4
IN4– 13 I Inverting input, channel 4
OUT1 1 O Output, channel 1
OUT2 7 O Output, channel 2
OUT3 8 O Output, channel 3
OUT4 14 O Output, channel 4
V+ 4 — Positive (highest) power supply
V– 11 — Negative (lowest) power supply
(1) I = input, O = output