SBOSAM4A December   2024  – June 2026 TLV9141 , TLV9142 , TLV9144

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information for Single Channel
    5. 5.5 Thermal Information for Dual Channel
    6. 5.6 Thermal Information for Quad Channel
    7. 5.7 Electrical Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Protection Circuitry
      2. 6.3.2 Common-Mode Voltage Range
      3. 6.3.3 EMI Rejection
      4. 6.3.4 Phase Reversal Protection
      5. 6.3.5 Electrical Overstress
      6. 6.3.6 Overload Recovery
      7. 6.3.7 Typical Specifications and Distributions
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Low-Side Current Measurement
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 TINA-TI (Free Software Download)
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.4 Thermal Information for Single Channel

THERMAL METRIC (1) TLV9141 UNIT
D
(SOIC)		 DBV
(SOT-23)		 DCK
(SC70)
8 PINS 5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 139.2 196.7 213.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 77.9 94.1 130.6 °C/W
RθJB Junction-to-board thermal resistance 88.4 63.3 72.6 °C/W
ψJT Junction-to-top characterization parameter 24.2 30.8 39.3 °C/W
ψJB Junction-to-board characterization parameter 87.2 62.9 72.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.