SBVS123C December   2008  – March 2025 TPS737-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Output Noise
      2. 6.3.2 Internal Current Limit
      3. 6.3.3 Enable Pin and Shutdown
      4. 6.3.4 Reverse Current
      5. 6.3.5 Thermal Protection
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input and Output Capacitor Requirements
        2. 7.2.2.2 Dropout Voltage
        3. 7.2.2.3 Transient Response
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Improve PSRR and Noise Performance
        2. 7.4.1.2 Power Dissipation
      2. 7.4.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.2.2.3 Transient Response

The low open-loop output impedance provided by the NMOS pass transistor in a voltage follower configuration allows operation without a 1µF output capacitor. As with any regulator, the addition of additional capacitance from the OUT pin to ground reduces undershoot magnitude but increases duration. In the adjustable version, the addition of a capacitor (CFB) between the OUT pin and the FB pin also improves transient response.

The TPS737-Q1 does not have an active pulldown when the output is overvoltage. This architecture allows for applications that connect higher voltage sources, such as alternate power supplies, to be connected to the output. This architecture results in an output overshoot of several percent if load current quickly drops to zero when a capacitor is connected to the output. Reduce the duration of overshoot by adding a load resistor. The overshoot decays at a rate determined by the output capacitor (COUT) and the internal and external load resistance. The rate of decay is given by Equation 4 and Equation 5.

(Fixed voltage version):

Equation 4. TPS737-Q1

(Adjustable voltage version):

Equation 5. TPS737-Q1