SBVS154A March   2012  – June 2025 TPS79633-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Undervoltage Lockout (UVLO)
      2. 6.3.2 Shutdown
      3. 6.3.3 Active Discharge (New Chip)
      4. 6.3.4 Thermal Protection
      5. 6.3.5 Regulator Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Exiting Dropout
      2. 7.1.2 External Capacitor Requirements
      3. 7.1.3 Board Layout Recommendation to Improve PSRR and Noise Performance
      4. 7.1.4 Regulator Mounting
      5. 7.1.5 Thermal Information
        1. 7.1.5.1 Power Dissipation
        2. 7.1.5.2 Estimating Junction Temperature
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Nomenclature
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

Figure 4-1 DCQ Package, 6-Pin SOT-223 (Top View)
Table 4-1 Pin Functions
PIN DESCRIPTION
NAME SOT223 (DCQ) TYPE
NR/NC 5 — Noise-reduction pin (legacy chip). Connecting an external capacitor to this pin bypasses noise generated by the internal band gap, improves power-supply rejection and reduces output noise. No connect pin (new chip). This pin is not internally connected. Connect to GND or leave floating.
EN 1 Input Enable pin. Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. EN can be connected to IN if not used.
GND 3, Tab — Device GND. Connect GND and TAB to the same ground on the board.
IN 2 Input Input pin. For best performance, place the nominal recommended value or larger ceramic capacitor from IN to GND; see the Recommended Operating Conditions table. Place the input capacitor as close to the input of the device as possible.
OUT 4 Output Regulated output. A 1µF or greater capacitor is required from OUT to ground for stability. Place the output capacitor as close to output of the device as possible; see the Recommended Operating Conditions table.