SBVS220C March   2013  – October 2026 TPS7A37

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Internal Current Limit
      2. 6.3.2 Enable Pin and Shutdown
      3. 6.3.3 Reverse Current
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Input and Output Capacitor Requirements
      2. 7.1.2 Output Noise
      3. 7.1.3 Dropout Voltage
      4. 7.1.4 Transient Response
    2. 7.2 Typical Applications
      1. 7.2.1 Typical Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Fixed-Voltage Version
      3. 7.2.3 Adjustable Operation
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
        2. 7.4.1.2 Thermal Considerations
        3. 7.4.1.3 Power Dissipation
        4. 7.4.1.4 Estimating Junction Temperature
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.2.1.2 Detailed Design Procedure

Due to the transients in this application input and output capacitors must be used. A CIN = COUT = 10µF capacitor has been selected.

The ESR of the chosen capacitor can be checked by looking the magnitude of the complex impedance over frequency. When |Zc| reaches a minimum the DC ESR is the value of |Zc| at that frequency. The ESR of the chosen capacitor is 10mΩ, which gives us a product of 10mΩ × 10µF = 100nΩ-F > 50nΩ-F, minimizing the ringing during transients.

As the VIN - VOUT change is only 300mV with a 100mA DC current, the expected junction temperature rise over the ambient, on a JEDEC standard board, is 67.2C/W × 0.3V × 0.1A = 2C.

To provide the best accuracy, R1 = 52.3kΩ and R2 = 30.1kΩ, and a 10nF CFF is used to reduce output noise.