SBVS430C April   2023  – August 2025 TPS3808E-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Voltage Thresholds
  6. 5 Pin Configuration and Functions
  7. 6 Specification
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagram
  8. 7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 SENSE Input
      2. 8.3.2 Selecting the RESET Delay Time
      3. 8.3.3 Manual RESET (MR) Input
      4. 8.3.4 RESET Output
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VDD(min))
      2. 8.4.2 Above Power-On Reset but Less Than VDD(min) (VPOR < VDD < VDD(min))
      3. 8.4.3 Below Power-On Reset (VDD < VPOR)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Immunity to SENSE Pin Voltage Transients
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Evaluation Modules
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.6 Timing Requirements

At 1.7V ≤ VDD ≤ 6V, CT = MR =  Open, RESET Voltage (VRESET) = 100kΩ to VDD, RESET load = 50pF, and over the operating free-air temperature range of -40°C to 125°C, unless otherwise noted. Typical values are at TJ = 25°C.
MIN NOM MAX UNIT
tD Reset time delay CT = Open 12 20 28 ms
tD Reset time delay CT = VDD 180 300 420 ms
tD Reset time delay CT = 130pF 0.75 1.25 1.75 ms
tD Reset time delay CT = 150nF 0.83 s
tPD Propagation detect delay(1)(2) 30 50 µs
tSD Startup delay(3) 300 µs
tGI (VIT-) Glitch Immunity undervoltage VIT-(UV), 5% Overdrive(1) 5 µs
tGI (MR) Glitch Immunity MR pin 50 ns
tPD (MR) Propagation delay from MR low to assert RESET 500 ns
(1) 5% Overdrive from threshold. Overdrive % = [VSENSE - VIT] / VIT; Where VIT stands for VIT-(UV)
(2) tPD measured from threshold trip point (VIT-(UV) or VIT+(OV)) to RESET VOL voltage
(3) During the power-on sequence, VDD must be at or above VDD (MIN) for at least tSD + tD before the output is in the correct state.