SBVS483 January   2026 TPS7A57-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Voltage Setting and Regulation
      2. 6.3.2 Low-Noise, Ultra-High Power-Supply Rejection Ratio (PSRR)
      3. 6.3.3 Programmable Soft-Start (NR/SS Pin)
      4. 6.3.4 Precision Enable and UVLO
      5. 6.3.5 Charge Pump Enable and BIAS Rail
      6. 6.3.6 Power-Good Pin (PG Pin)
      7. 6.3.7 Active Discharge
      8. 6.3.8 Thermal Shutdown Protection (TSD)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
      4. 6.4.4 Current-Limit Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1  Precision Enable (External UVLO)
      2. 7.1.2  Undervoltage Lockout (UVLO) Operation
        1. 7.1.2.1 IN Pin UVLO
        2. 7.1.2.2 BIAS UVLO
        3. 7.1.2.3 Typical UVLO Operation
        4. 7.1.2.4 UVLO(IN) and UVLO(BIAS) Interaction
      3. 7.1.3  Dropout Voltage (VDO)
      4. 7.1.4  Input and Output Capacitor Requirements (CIN and COUT)
      5. 7.1.5  Recommended Capacitor Types
      6. 7.1.6  Soft-Start, Noise Reduction (NR/SS Pin), and Power-Good (PG Pin)
      7. 7.1.7  Optimizing Noise and PSRR
      8. 7.1.8  Adjustable Operation
      9. 7.1.9  Load Transient Response
      10. 7.1.10 Current Limit and Foldback Behavior
      11. 7.1.11 Charge Pump Operation
      12. 7.1.12 Sequencing
      13. 7.1.13 Power-Good Functionality
      14. 7.1.14 Output Impedance
      15. 7.1.15 Paralleling for Higher Output Current and Lower Noise
      16. 7.1.16 Power Dissipation (PD)
      17. 7.1.17 Estimating Junction Temperature
      18. 7.1.18 TPS7A57EVM-056 Thermal Analysis
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

7.1.14 Output Impedance

Output impedance can be modeled, as shown in Figure 7-13, as an ideal voltage source followed by a series R (ROUT) and series L (LOUT) output.

TPS7A57-Q1 Output Impedance ModelFigure 7-13 Output Impedance Model

Output impedance curves are measured using the EVM and are provided for the following conditions:

  1. Figure 7-14, Figure 7-15, and Figure 7-16 are provided for the 5.5VIN, 5VOUT, and IOUT = 200mA, 500mA, and 5A conditions
  2. Figure 7-17 is provided for the 0.9VIN, 0.5VOUT, and IOUT = 4.6A conditions
  3. Figure 7-18 to Figure 7-21 are provided for the 0.75 -VIN, 0.5VOUT, 3VBIAS, and IOUT = 20mA, 200mA, 500mA, and 1A conditions.

TPS7A57-Q1 VIN = 5.5V, VOUT = 5V, VBIAS = 8V, CP_EN = 0, IOUT = 200mAFigure 7-14 VIN = 5.5V, VOUT = 5V, VBIAS = 8V, CP_EN = 0, IOUT = 200mA
TPS7A57-Q1 VIN = 5.5V, VOUT = 5V, VBIAS = 8V, CP_EN = 0, IOUT = 5AFigure 7-16 VIN = 5.5V, VOUT = 5V, VBIAS = 8V, CP_EN = 0, IOUT = 5A
TPS7A57-Q1 VIN = 0.75V, VBIAS = 3V, VOUT = 0.5V , CP_EN = 0, IOUT = 20mAFigure 7-18 VIN = 0.75V, VBIAS = 3V, VOUT = 0.5V , CP_EN = 0, IOUT = 20mA
TPS7A57-Q1 VIN = 0.75V, VBIAS = 3V, VOUT = 0.5V, CP_EN = 0, IOUT = 500mAFigure 7-20 VIN = 0.75V, VBIAS = 3V, VOUT = 0.5V, CP_EN = 0, IOUT = 500mA
TPS7A57-Q1 VIN = 5.5V, VOUT = 5V, VBIAS = 8V, CP_EN = 0, IOUT = 500mAFigure 7-15 VIN = 5.5V, VOUT = 5V, VBIAS = 8V, CP_EN = 0, IOUT = 500mA
TPS7A57-Q1 VIN = 0.9V, VBIAS = 3V, VOUT = 0.5V , CP_EN = 0, IOUT = 4.6AFigure 7-17 VIN = 0.9V, VBIAS = 3V, VOUT = 0.5V , CP_EN = 0, IOUT = 4.6A
TPS7A57-Q1 VIN = 0.75V, VBIAS = 3V, VOUT = 0.5V, CP_EN = 0, IOUT = 100mAFigure 7-19 VIN = 0.75V, VBIAS = 3V, VOUT = 0.5V, CP_EN = 0, IOUT = 100mA
TPS7A57-Q1 VIN = 0.75V, VBIAS = 3V, VOUT = 0.5V, CP_EN = 0, IOUT = 1AFigure 7-21 VIN = 0.75V, VBIAS = 3V, VOUT = 0.5V, CP_EN = 0, IOUT = 1A

Table 7-6 provides a summary of the tested conditions described in this section.

Table 7-6 Model for Tested Conditions Summary
VINVOUTVBIASIOUTCP_ENROUTLOUT
0.75V0.5V3V20mAOff200μΩ0.5nH
0.75V0.5V3V200mAOff200μΩ0.5nH
0.75V0.5V3V500mAOff200μΩ0.5nH
0.75V0.5V3V1AOff200μΩ0.5nH
0.9V0.5V3V4.6AOff200μΩ0.5nH
5.5V5V8V200mAOff400μΩ0.5nH
5.5V5V8V500mAOff300μΩ0.5nH
5.5V5V8V5AOff200μΩ0.5nH