SBVS483 January   2026 TPS7A57-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Voltage Setting and Regulation
      2. 6.3.2 Low-Noise, Ultra-High Power-Supply Rejection Ratio (PSRR)
      3. 6.3.3 Programmable Soft-Start (NR/SS Pin)
      4. 6.3.4 Precision Enable and UVLO
      5. 6.3.5 Charge Pump Enable and BIAS Rail
      6. 6.3.6 Power-Good Pin (PG Pin)
      7. 6.3.7 Active Discharge
      8. 6.3.8 Thermal Shutdown Protection (TSD)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
      4. 6.4.4 Current-Limit Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1  Precision Enable (External UVLO)
      2. 7.1.2  Undervoltage Lockout (UVLO) Operation
        1. 7.1.2.1 IN Pin UVLO
        2. 7.1.2.2 BIAS UVLO
        3. 7.1.2.3 Typical UVLO Operation
        4. 7.1.2.4 UVLO(IN) and UVLO(BIAS) Interaction
      3. 7.1.3  Dropout Voltage (VDO)
      4. 7.1.4  Input and Output Capacitor Requirements (CIN and COUT)
      5. 7.1.5  Recommended Capacitor Types
      6. 7.1.6  Soft-Start, Noise Reduction (NR/SS Pin), and Power-Good (PG Pin)
      7. 7.1.7  Optimizing Noise and PSRR
      8. 7.1.8  Adjustable Operation
      9. 7.1.9  Load Transient Response
      10. 7.1.10 Current Limit and Foldback Behavior
      11. 7.1.11 Charge Pump Operation
      12. 7.1.12 Sequencing
      13. 7.1.13 Power-Good Functionality
      14. 7.1.14 Output Impedance
      15. 7.1.15 Paralleling for Higher Output Current and Lower Noise
      16. 7.1.16 Power Dissipation (PD)
      17. 7.1.17 Estimating Junction Temperature
      18. 7.1.18 TPS7A57EVM-056 Thermal Analysis
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

7.1.11 Charge Pump Operation

As discussed in the Charge Pump Enable and BIAS Rail section, the internal charge pump can be enabled or disabled using the CP_EN pin, allowing operation as low as 1.1V without a BIAS rail.

The CP_EN pin voltage threshold and hysteresis are defined in the Electrical Characteristics table.

Depending on the circuit implementation, the internal charge pump is powered from either the IN or the BIAS rails. This pin is not designed to be digitally controlled with a digital I/O pin, but is instead intended to be tied on the printed circuit board (PCB) to an analog rail.

Although not intended to be controlled dynamically, the CP_EN pin can be controlled by using a low impedance source and verifying adequate sequencing between EN and CP_EN because the CP_EN pin is latched when the EN pin is turned on and only an EN reset or a power cycle clears and resets the CP_EN latch.

#IMAGE_UKS_5ZB_D5B shows the switching frequency of the charge pump at no-load and full load.

TPS7A57-Q1 Charge Pump NoiseFigure 7-11 Charge Pump Noise