SBVU068 august   2023 TPS7A78

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Setup
      1. 2.1.1 Full-Bridge (FB) Test Equipment Connection
      2. 2.1.2 Half-Bridge (HB) Test Equipment Connection
    2. 2.2 Jumper Information
      1. 2.2.1  J1: LDO_IN
      2. 2.2.2  J2: Line VAC
      3. 2.2.3  J3: LDO_OUT
      4. 2.2.4  J4: LDO_IN Sense
      5. 2.2.5  J5: SCIN
      6. 2.2.6  J6: LDO_OUT Sense
      7. 2.2.7  J7: LDO_OUT/GND
      8. 2.2.8  J8: LDO_IN/GND
      9. 2.2.9  J9, J11, J13: GND
      10. 2.2.10 J10: Neutral VAC
      11. 2.2.11 J12: Second Surge Resistor Jumper
      12. 2.2.12 J14: Full-Bridge (FB) and Half-Bridge(HB) Configurations
      13. 2.2.13 J15: LDO Pin test header
      14. 2.2.14 J16 and J18: Power-Good (PG) and Power-Fail (PF) Signals
      15. 2.2.15 J17: Coin Cell Buffer VCC Jumper
    3. 2.3 Test Points
  7. 3Implementation Results
    1. 3.1 Performance Data and Results
  8. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 PCB Layouts
    3. 4.3 Bill of Materials (BOM)
  9. 5Compliance Information
    1. 5.1 Compliance and Certifications
      1. 5.1.1 Passing Pre-Compliance Conducted Emission Test Results Using Capacitors and Resistors in the Input Filter
      2. 5.1.2 Passing Pre-Compliance Conducted Emission Test Results Using Capacitors, Resistors and Inductors in the Input Filter
    2. 5.2 Surge Testing
    3. 5.3 EFT Compliance
    4. 5.4 ESD Compliance
  10. 6Additional Information
    1. 6.1 Trademarks

2.3 Test Points

Table 2-1 Test Point Functions
TEST POINTS NAME DESCRIPTION
TP1 AC+ AC supply line input to the device after the cap-drop capacitor and surge resistor.
TP2 LDO_IN Charge-pump output pin
TP3 SC_IN Rectified DC voltage pin; see the TPS7A78 Application and Implementation section for the proper setting of your application requirement.
TP4 PFD Power-fail detect pin.
TP5 LDO_OUT Regulated DC output pin.
TP6 AC- AC supply neutral input to the device after the cap-drop capacitor and surge resistor.
TP7 GND Device GND connected to the thermal pad.
TP8 GND
TP9 PF Power-fail pin.
TP10 Buffer VCC VCC pin of the buffer circuitry.
TP11 PG Power-good pin.