SCAS521H August   1995  – June 2025 SN54AC74 , SN54AC74-SP , SN74AC74

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Timing Requirements, VCC = 3.3 V ± 0.3 V
    6. 5.6 Timing Requirements, VCC = 5 V ± 0.5 V
    7. 5.7 Switching Characteristics, VCC = 3.3 V ± 0.3 V
    8. 5.8 Switching Characteristics, VCC = 5 V ± 0.5 V
    9. 5.9 Operating Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 Latching Logic
      3. 7.3.3 Standard CMOS Inputs
      4. 7.3.4 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

SN54AC74 SN74AC74 SN54AC74 J or W Package; SN74AC74 D, DB, N, NS, or PW Package (Top View)Figure 4-1 SN54AC74 J or W Package; SN74AC74 D, DB, N, NS, or PW Package (Top View)
SN54AC74 SN74AC74 BQA Package,14-Pin WQFN With Exposed Thermal Pad(Top View)Figure 4-3 BQA Package,14-Pin WQFN With Exposed Thermal Pad(Top View)
SN54AC74 SN74AC74 SN54AC74 FK Package (Top View)Figure 4-2 SN54AC74 FK Package (Top View)
PIN TYPE(1) DESCRIPTION
NAME NO.
1 CLR 1 I Channel 1, Clear Input, Active Low
1D 2 I Channel 1, Data Input
1CLK 3 I Channel 1, Positive edge triggered clock input
1 PRE 4 I Channel 1, Preset Input, Active Low
1Q 5 O Channel 1, Output
1 Q 6 O Channel 1, Inverted Output
GND 7 G Ground
2 Q 8 O Channel 2, Inverted Output
2Q 9 O Channel 2, Output
2 PRE 10 I Channel 2, Preset Input, Active Low
2CLK 11 I Channel 2, Positive edge triggered clock input
2D 12 I Channel 2, Data Input
2 CLR 13 I Channel 2, Clear Input, Active Low
VCC 14 P Positive Supply
Thermal Pad(2) —

Thermal Pad
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power
(2) BQA package only