SN74AC74 Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset | TI.com

SN74AC74
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Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset

Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset - SN74AC74
Datasheet
 

Description

The ’AC74 devices are dual positive-edge-triggered D-type flip-flops.

A low level at the preset (PRE)\ or clear (CLR)\ input sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at D can be changed without affecting the levels at the outputs.

Features

  • 2-V to 6-V VCC Operation
  • Inputs Accept Voltages to 6 V
  • Max tpd of 10 ns at 5 V

Parametrics

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Part number Order Technology Family Input type Output type VCC (Min) (V) VCC (Max) (V) IOL (Max) (mA) IOH (Max) (mA) Rating Package Group
SN74AC74 Order now AC     CMOS     CMOS     2     6     24     -24     Catalog     PDIP | 14
SOIC | 14
SO | 14
SSOP | 14
TSSOP | 14    
SN54AC74 Samples not available AC     CMOS     CMOS     2     6     24     -24     Military     CDIP | 14
CFP | 14
LCCC | 20