SCAS526E August   1995  – July 2025 SN54ACT10 , SN74ACT10

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Switching Characteristics
    6. 5.6 Operating Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 TTL-Compatible CMOS Inputs
      3. 7.3.3 Clamp Diode Structure
  9. 8 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Power Considerations
        2. 9.2.1.2 Input Considerations
        3. 9.2.1.3 Output Considerations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
      4. 9.2.4 Power Supply Recommendations
      5. 9.2.5 Layout
        1. 9.2.5.1 Layout Guidelines
        2. 9.2.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

3 Description

The SNx4ACT10 devices contain three independent 3-input NAND gates. The devices perform the Boolean functions Y = A • B • C or Y = A + B + C in positive logic.

Device Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3)
SN54ACT10 FK (LCCC, 20) 8.89mm × 8.89mm 8.89mm × 8.89mm
J (CDIP, 14) 19.55mm × 7.60mm 19.55mm × 6.71mm
W (CFP, 14) 9.21mm × 7.11mm 9.21mm × 6.29mm
SN74ACT10 D (SOIC, 14) 8.65mm × 6mm 8.65mm × 3.9mm
N (PDIP, 14) 19.3mm × 9.4mm 19.3mm × 6.35mm
DB (SSOP, 14) 6.2mm x 7.8mm 6.2mm x 5.3mm
PW (TSSOP, 14) 5mm × 6.4mm 5mm × 4.4mm
BQA (WQFN, 14) 3mm × 2.5mm 3mm × 2.5mm
(1) For more information, see the Mechanical, Packaging, and Orderable Information.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
(3) The body size (length × width) is a nominal value and does not include pins.
SN54ACT10 SN74ACT10 Logic Diagram, Each Gate (Positive Logic) Logic Diagram, Each Gate (Positive Logic)