SCAS844H August   2007  – July 2025 CDCE949 , CDCEL949

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 EEPROM Specification
    7. 5.7 Timing Requirements: CLK_IN
    8. 5.8 Timing Requirements: SDA/SCL
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Terminal Setting
      2. 7.3.2 Default Device Setting
      3. 7.3.3 SDA/SCL Serial Interface
      4. 7.3.4 Data Protocol
    4. 7.4 Device Functional Modes
      1. 7.4.1 SDA/SCL Hardware Interface
    5. 7.5 Programming
  9. 8 Register Maps
    1. 8.1 SDA/SCL Configuration Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Spread Spectrum Clock (SSC)
        2. 9.2.2.2 PLL Frequency Planning
        3. 9.2.2.3 Crystal Oscillator Start-Up
        4. 9.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 9.2.2.5 Unused Inputs and Outputs
        6. 9.2.2.6 Switching Between XO and VCXO Mode
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Related Documentation
    3. 10.3 Related Links
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.3.2 Default Device Setting

Figure 7-1 shows the preconfiguration (the input frequency is passed through to the output as a default) of the internal EEPROM of CDCEx949. This preconfiguration allows the device to operate in default mode without the extra production step of programming. The default setting appears after power is supplied or after power-down or power-up sequence until the setting is re-programmed by the user to a different application configuration. A new register setting is programmed through the serial SDA/SCL Interface.

CDCE949 CDCEL949 Default Device SettingFigure 7-1 Default Device Setting

Table 7-4 shows the factory default setting for the Control Terminal Register (external control pins). In normal operation, all 8 register settings are available, but in the default configuration only the first two settings (0 and 1) can be selected with S0, as S1 and S2 configured as programming pins in default mode.

Table 7-4 Factory Default Setting for Control Terminal Register
Y1PLL1 SETTINGPLL2 SETTINGPLL3 SETTINGPLL3 SETTING
EXTERNAL CONTROL PINS(1)OUTPUT
SELECT		FREQ.
SELECT		SSC
SEL.		OUTPUT
SELECT		FREQ.
SELECT		SSC
SEL.		OUTPUT
SELECT		FREQ.
SELECT		SSC
SEL.		OUTPUT
SELECT		FREQ.
SELECT		SSC
SEL.		OUTPUT
SELECT
S2S1S0Y1FS1SSC1Y2Y3FS2SSC2Y4Y5FS3SSC3Y6Y7FS4SSC4Y8Y9
SCL (I2C)SDA (I2C)03-statefVCO1_0off3-statefVCO2_0off3-statefVCO3_0off3-statefVCO4_0off3-state
SCL (I2C)SDA (I2C)1enabledfVCO1_0offenabledfVCO2_0offenabledfVCO3_0offenabledfVCO4_0offenabled
(1) In default mode or when programmed respectively, S1 and S2 act as serial programming interface, SDA/SCL. They do not have any control-pin function but they are internally interpreted as if S1 = 0 and S2 = 0. However, S0 is a control-pin which in the default mode switches all outputs ON or OFF (as previously predefined).