SCAS898C May   2010  – May 2026 CDCLVD1204

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 LVDS Output Termination
      2. 7.4.2 Input Termination
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

6 Parameter Measurement Information

CDCLVD1204 LVDS Output DC Configuration During Device Test Figure 6-1 LVDS Output DC Configuration During Device Test
CDCLVD1204 LVDS Output AC Configuration During Device Test Figure 6-2 LVDS Output AC Configuration During Device Test
CDCLVD1204 DC Coupled LVCMOS Input During Device Test Figure 6-3 DC Coupled LVCMOS Input During Device Test
CDCLVD1204 Output Voltage and Rise/Fall Time Figure 6-4 Output Voltage and Rise/Fall Time
CDCLVD1204 Output Skew and Part-to-Part Skew
  1. Output skew is calculated as the greater of the following: As the difference between the fastest and the slowest tPLHn or the difference between the fastest and the slowest tPHLn (n = 0, 1, 2, 3).
  2. Part-to-part skew is calculated as the greater of the following: As the difference between the fastest and the slowest tPLHn or the difference between the fastest and the slowest tPHLn across multiple devices (n = 0, 1, 2, 3).
Figure 6-5 Output Skew and Part-to-Part Skew
CDCLVD1204 Output Overshoot and Undershoot Figure 6-6 Output Overshoot and Undershoot
CDCLVD1204 Output AC Common Mode Figure 6-7 Output AC Common Mode