Product details

Function Differential Additive RMS jitter (typ) (fs) 171 Output frequency (max) (MHz) 800 Number of outputs 4 Output supply voltage (V) 2.5 Core supply voltage (V) 2.5 Output skew (ps) 20 Features 2:4 fanout, Universal inputs Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVDS Input type LVCMOS, LVDS, LVPECL
Function Differential Additive RMS jitter (typ) (fs) 171 Output frequency (max) (MHz) 800 Number of outputs 4 Output supply voltage (V) 2.5 Core supply voltage (V) 2.5 Output skew (ps) 20 Features 2:4 fanout, Universal inputs Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVDS Input type LVCMOS, LVDS, LVPECL
VQFN (RGT) 16 9 mm² 3 x 3
  • 2:4 Differential Buffer
  • Low Additive Jitter: <300 fs RMS in 10-kHz to 20-MHz
  • Low Output Skew of 20 ps (Maximum)
  • Universal Inputs Accept LVDS, LVPECL, and LVCMOS
  • Selectable Clock Inputs Through Control Pin
  • 4 LVDS Outputs, ANSI EAI/TIA-644A Standard Compatible
  • Clock Frequency: Up to 800 MHz
  • Device Power Supply: 2.375 V to 2.625 V
  • LVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled Inputs
  • Industrial Temperature Range: –40°C to 85°C
  • Packaged in 3 mm × 3 mm, 16-Pin VQFN (RGT)
  • ESD Protection Exceeds 3 kV HBM, 1 kV CDM
  • APPLICATIONS
    • Telecommunications and Networking
    • Medical Imaging
    • Test and Measurement Equipment
    • Wireless Communications
    • General Purpose Clocking

All other trademarks are the property of their respective owners

  • 2:4 Differential Buffer
  • Low Additive Jitter: <300 fs RMS in 10-kHz to 20-MHz
  • Low Output Skew of 20 ps (Maximum)
  • Universal Inputs Accept LVDS, LVPECL, and LVCMOS
  • Selectable Clock Inputs Through Control Pin
  • 4 LVDS Outputs, ANSI EAI/TIA-644A Standard Compatible
  • Clock Frequency: Up to 800 MHz
  • Device Power Supply: 2.375 V to 2.625 V
  • LVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled Inputs
  • Industrial Temperature Range: –40°C to 85°C
  • Packaged in 3 mm × 3 mm, 16-Pin VQFN (RGT)
  • ESD Protection Exceeds 3 kV HBM, 1 kV CDM
  • APPLICATIONS
    • Telecommunications and Networking
    • Medical Imaging
    • Test and Measurement Equipment
    • Wireless Communications
    • General Purpose Clocking

All other trademarks are the property of their respective owners

The CDCLVD1204 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 pairs of differential LVDS clock outputs (OUT0 through OUT3) with minimum skew for clock distribution. The CDCLVD1204 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD1204 is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage, VAC_REF, must be applied to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static). The part supports a fail safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 2.5-V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1204 is packaged in small, 16-pin, 3-mm × 3-mm VQFN package.

The CDCLVD1204 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 pairs of differential LVDS clock outputs (OUT0 through OUT3) with minimum skew for clock distribution. The CDCLVD1204 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD1204 is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage, VAC_REF, must be applied to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static). The part supports a fail safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 2.5-V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1204 is packaged in small, 16-pin, 3-mm × 3-mm VQFN package.

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Technical documentation

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Type Title Date
* Data sheet CDCLVD1204 2:4 Low Additive Jitter LVDS Buffer datasheet (Rev. B) PDF | HTML 05 Oct 2016
Application note Sine to Square Wave Conversion Using Clock Buffers PDF | HTML 03 Sep 2024
Application note Clocking Design Guidelines: Unused Pins 19 Nov 2015
User guide Low-Additive Jitter, Four LVDS Outputs Clock Buffer Evaluation Board 14 Jun 2010

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

CDCLVD1204EVM — CDCLVD1204 Evaluation Module

The CDCLVD1204/CDCLVD2102 are high-performance, low-additive jitter clock buffers. They have twouniversal input buffers that support single-ended or differential clock inputs and are selectable through a control pin (for CDCLVD1204 only). The devices also feature on-chip bias generators that can (...)
User guide: PDF
Not available on TI.com
Simulation model

CDCLVD1204 IBIS Model (Rev. B)

SLLM089B.ZIP (14 KB) - IBIS Model
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Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
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PLLATINUMSIM-SW PLLatinum Sim Tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

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