CDCLVD1204

ACTIVE

Low Jitter, 2-Input Selectable 1:4 Universal-to-LVDS Buffer

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Product details

Parameters

Function Differential Additive RMS jitter (Typ) (fs) 171 Output frequency (Max) (MHz) 800 Number of outputs 4 VCC out (V) 2.5 VCC core (V) 2.5 Output skew (ps) 20 Features 2:4 fanout, Universal inputs Operating temperature range (C) -40 to 85 Rating Catalog Output type LVDS Input type LVCMOS, LVDS, LVPECL open-in-new Find other Clock buffers

Package | Pins | Size

VQFN (RGT) 16 9 mm² 3 x 3 open-in-new Find other Clock buffers

Features

  • 2:4 Differential Buffer
  • Low Additive Jitter: <300 fs RMS in 10-kHz to 20-MHz
  • Low Output Skew of 20 ps (Maximum)
  • Universal Inputs Accept LVDS, LVPECL, and LVCMOS
  • Selectable Clock Inputs Through Control Pin
  • 4 LVDS Outputs, ANSI EAI/TIA-644A Standard Compatible
  • Clock Frequency: Up to 800 MHz
  • Device Power Supply: 2.375 V to 2.625 V
  • LVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled Inputs
  • Industrial Temperature Range: –40°C to 85°C
  • Packaged in 3 mm × 3 mm, 16-Pin VQFN (RGT)
  • ESD Protection Exceeds 3 kV HBM, 1 kV CDM
  • APPLICATIONS
    • Telecommunications and Networking
    • Medical Imaging
    • Test and Measurement Equipment
    • Wireless Communications
    • General Purpose Clocking

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Description

The CDCLVD1204 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 pairs of differential LVDS clock outputs (OUT0 through OUT3) with minimum skew for clock distribution. The CDCLVD1204 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD1204 is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage, VAC_REF, must be applied to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static). The part supports a fail safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 2.5-V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1204 is packaged in small, 16-pin, 3-mm × 3-mm VQFN package.

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Technical documentation

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Type Title Date
* Datasheet CDCLVD1204 2:4 Low Additive Jitter LVDS Buffer datasheet (Rev. B) Oct. 05, 2016
Selection guides Clock & Timing Solutions (Rev. C) Jan. 19, 2017
Application notes Clocking Design Guidelines: Unused Pins Nov. 19, 2015
Selection guides Power, Interface and Clock Solutions for the TED Spartan-6 FPGA (Rev. A) May 29, 2014
User guides Low-Additive Jitter, Four LVDS Outputs Clock Buffer Evaluation Board Jun. 14, 2010

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
$149.00
Description
The CDCLVD1204/CDCLVD2102 are high-performance, low-additive jitter clock buffers. They have two universal input buffers that support single-ended or differential clock inputs and are selectable through a control pin (for CDCLVD1204 only). The devices also feature on-chip bias generators that can (...)
Features
  • Easy-to-use evaluation board to fan out low-phase noise clocks
  • Easy device setup
  • Fast configuration
  • Control pins configurable through jumpers
  • Board powered at 2.5 V
  • Single-ended or differential input clocks
  • Device supports four LVDS outputs, EVM supports two LVDS outputs

Design tools & simulation

SIMULATION MODELS Download
SLLM089B.ZIP (14 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
VQFN (RGT) 16 View options

Ordering & quality

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