SCAS898C May   2010  – May 2026 CDCLVD1204

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 LVDS Output Termination
      2. 7.4.2 Input Termination
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

1 Features

  • 2:4 differential buffer
  • Low additive jitter: <300fs RMS in 10kHz to
    20MHz
  • Low output skew of 20ps (maximum)
  • Universal inputs accept LVDS, LVPECL, and LVCMOS
  • Selectable clock inputs through control pin
  • 4 LVDS outputs, ANSI EIA/TIA-644A standard compatible
  • Clock frequency: up to 800MHz
  • Device power supply: 2.375V to 2.625V
  • LVDS reference voltage, VAC_REF, available for capacitive coupled inputs
  • Industrial temperature range: –40°C to 85°C
  • Packaged in 3mm × 3mm, 16-Pin VQFN (RGT)
  • ESD protection exceeds 3kV HBM, 1kV CDM