SCAS962B November   2023  – September 2024 SN74AC8541

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
    4. 6.4 Feature Description
      1. 6.4.1 Balanced CMOS 3-State Outputs
      2. 6.4.2 CMOS Schmitt-Trigger Inputs
      3. 6.4.3 Clamp Diode Structure
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
    3. 7.3 Design Requirements
      1. 7.3.1 Power Considerations
      2. 7.3.2 Input Considerations
      3. 7.3.3 Output Considerations
    4. 7.4 Detailed Design Procedure
    5. 7.5 Application Curves
    6. 7.6 Power Supply Recommendations
    7. 7.7 Layout
      1. 7.7.1 Layout Guidelines
      2. 7.7.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
Specification Description Condition MIN MAX UNIT
VCC Supply voltage 1.5 6 V
VI(1) Input Voltage 0 VCC V
VO Output Voltage 0 VCC V
IOH High-level output current VCC = 1.8 V -1 mA
VCC = 2.5 V -2
VCC = 3.3 V -12
VCC = 5 V -24
IOL Low-level output current VCC = 1.8 V 1 mA
VCC = 2.5 V 2
VCC = 3.3 V 12
VCC = 5 V 24
Δt/Δv Input transition rise or fall rate 1.5 V ≤ VCC ≤ 5.5 V Unlimited
3 V < VCC ≤ 5.5 V Unlimited
TA Operating free-air temperature -40 125 °C
(1) All unused inputs of the device must be held at VCC or GND for proper device operation. Refer to the TI application report Implications of Slow or Floating CMOS Inputs.