SCASE16A
September 2024 – June 2025
SN74AC2G100
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Timing Characteristics
5.7
Switching Characteristics
5.8
Typical Characteristics
6
Parameter Measurement Information
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Balanced CMOS Push-Pull Outputs
7.3.2
CMOS Schmitt-Trigger Inputs
7.3.3
Latching Logic
7.3.4
Clamp Diode Structure
7.4
Device Functional Modes
7.5
Combinatorial Logic Configurations
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.1.1
Power Considerations
8.2.1.2
Input Considerations
8.2.1.3
Output Considerations
8.2.2
Detailed Design Procedure
8.3
Application Curves
8.4
Power Supply Recommendations
8.5
Layout
8.5.1
Layout Guidelines
8.5.2
Layout Example
9
Device and Documentation Support
9.1
Receiving Notification of Documentation Updates
9.2
Support Resources
9.3
Trademarks
9.4
Electrostatic Discharge Caution
9.5
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
7.4
Device Functional Modes
Table 7-1 Function Table
INPUTS
OUTPUT
A
B
C
D
Y
L
L
L
L
L
L
L
L
H
H
L
L
H
L
L
L
L
H
H
H
L
H
L
L
L
L
H
L
H
H
L
H
H
L
H
L
H
H
H
L
H
L
L
L
H
H
L
L
H
L
H
L
H
L
L
H
L
H
H
H
H
H
L
L
H
H
H
L
H
L
H
H
H
L
H
H
H
H
H
L
Table 7-2 Function Table
INPUTS
(1)
(2)
OUTPUT
CLR
CLK
D
Q
L
X
X
L
H
↑
H
H
H
↑
L
L
H
L
X
Q
0
(1)
H = high voltage level, L = low voltage level, X = don't care
(2)
This configuration is nonstable; that is, it does not persist when CLR returns to its inactive (high) level.