SCASE80A September   2025  – January 2026 TPUL2T323-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7.     13
    8. 5.7 Switching Characteristics
    9. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 State Machine Description
        1. 7.1.1.1 Ready
        2. 7.1.1.2 RC Measurement Cycle
          1. 7.1.1.2.1 Discharge
          2. 7.1.1.2.2 Monitor
          3. 7.1.1.2.3 Timer Count Decision
          4. 7.1.1.2.4 Cycle Count Decision
          5. 7.1.1.2.5 Increment Cycle Counter
          6. 7.1.1.2.6 Reset Timer Counter
          7. 7.1.1.2.7 Save Timer Count
        3. 7.1.1.3 Digital Timer Cycle
          1. 7.1.1.3.1 Reset Timer Counter
          2. 7.1.1.3.2 Delay
          3. 7.1.1.3.3 Increment Cycle Counter
          4. 7.1.1.3.4 Cycle Count Decision
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Naming Convention
      2. 7.3.2  Retriggerable One-Shot
      3. 7.3.3  Extended RC Timed One-Shot
      4. 7.3.4  Balanced CMOS Push-Pull Outputs
      5. 7.3.5  CMOS Schmitt-Trigger Inputs
      6. 7.3.6  Latching Logic with Known Power-Up State
      7. 7.3.7  Partial Power Down (Ioff)
      8. 7.3.8  Reduced Input Threshold Voltages
      9. 7.3.9  Wettable Flanks
      10. 7.3.10 Clamp Diode Structure
    4. 7.4 Device Functional Modes
      1. 7.4.1 Off-State Operation
      2. 7.4.2 Startup Operation
      3. 7.4.3 On-State Operation
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application - Edge Detector
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Timing Components
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
        4. 8.2.1.4 Power Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Typical Application - Delayed Pulse Generator
      1. 8.3.1 Application Curves
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
7.1.1.2.6 Reset Timer Counter
  • Behavior
    • Timer counter value cleared
    • Active oscillator and clock frequency divider change based on new cycle counter value. See Table 7-1 table.
    • RC = High
    • Q = High
    • Q = Low
  • Transitions
    • In
      • From increment cycle counter state, task complete
    • Out
      • To ready state, clear active
      • To RC measurement cycle, trigger
      • To discharge state, task complete
Table 7-1 Timer Counter Clock Frequency
Cycle Active Oscillator Frequency Divider Counter Clock Maximum Output Pulse Width(1)
Frequency(1) Period(1)
1 10MHz(2) 1 13.5MHz 74ns 311ms
2 1MHz(3) 1 1.47MHz 680ns 2.85s
3 1MHz(3) 2 735kHz 1.36µs 5.71s
4 1MHz(3) 4 368kHz 2.72µs 11.4s
5 1MHz(3) 8 184kHz 5.44µs 22.8s
6 1MHz(3) 16 91.9kHz 10.9µs 45.7s
7 1MHz(3) 32 45.9kHz 21.8µs 91.3s
8 1MHz(3) 64 23.0kHz 43.5µs 183s
9 1MHz(3) 128 11.5kHz 87.1µs 365s
10 1MHz(3) 256 5.74kHz 174µs 730s
11 1MHz(3) 512 2.87kHz 348µs 1461s
12 1MHz(3) 1024 1.44kHz 697µs 2922s(4)
(1) Typical values
(2) 10MHz oscillator can vary from 7.8MHz to 18.9MHz
(3) 1MHz oscillator can vary from 1.1MHz to 1.9MHz
(4) Maximum digitally timed output pulse width can vary from 2253s to 3892s; total pulse width can increase beyond the maximum due to analog RC charge time