SCASE97 May   2025 SN74LVC595A-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 Balanced CMOS 3-State Outputs
      3. 7.3.3 Standard CMOS Inputs
      4. 7.3.4 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

5.7 Timing Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER DESCRIPTION CONDITION VCC -40°C to 125°C UNIT
MIN MAX
fclock Clock frequency 1.2V ± 0.1V 20 MHz
1.5V ± 0.12V 100
fclock Clock frequency 1.8V ± 0.15V 104 MHz
2.5V ± 0.2V 115
2.7V 105
3.3V ± 0.3V 104
tW Pulse duration SRCLK high or low 1.2V ± 0.1V 20 nS
1.5V ± 0.12V 7
RCLK high or low 1.2V ± 0.1V 20
1.5V ± 0.12V 7
SRCLR low 1.2V ± 0.1V 7 nS
1.5V ± 0.12V 7 nS
tW Pulse duration SRCLK high or low 1.8V ± 0.15V 7 nS
2.5V ± 0.2V 5.5
2.7V 5
3.3V ± 0.3V 4.5
RCLK high or low 1.8V ± 0.15V 7
2.5V ± 0.2V 5.5
2.7V 5
3.3V ± 0.3V 4.5
SRCLR low 1.8V ± 0.15V 5.5
nS
2.5V ± 0.2V 4.5
nS
2.7V 3
nS
3.3V ± 0.3V 3
nS
tSU Setup time SER before SRCLK↑ 1.2V ± 0.1V 21 nS
1.5V ± 0.12V 5.5
SRCLK↑ before RCLK↑ 1.2V ± 0.1V 46
1.5V ± 0.12V 9.5
SRCLR low before SRCLK↑ 1.2V ± 0.1V 25.4
nS
1.5V ± 0.12V 9.25
nS
SRCLR high (inactive) before SRCLK↑ 1.2V ± 0.1V 12.6
nS
1.5V ± 0.12V 5.5
nS
SRCLR high (inactive) before RCLK↑ 1.2V ± 0.1V 25.4
nS
1.5V ± 0.12V 9.25
nS
tSU Setup time before CLK↑ SER before SRCLK↑ 1.8V ± 0.15V 5.5 nS
2.5V ± 0.2V 4.5
2.7V 2.5
3.3V ± 0.3V 2.5
SRCLK↑ before RCLK↑ 1.8V ± 0.15V 6
2.5V ± 0.2V 3.5
2.7V 2.5
3.3V ± 0.3V 2.5
SRCLR low before SRCLK↑ 1.8V ± 0.15V 8.5
nS
2.5V ± 0.2V 5.5
nS
2.7V 4.5
nS
3.3V ± 0.3V 4.5
nS
SRCLR high (inactive) before SRCLK↑ 1.8V ± 0.15V 5.5
nS
2.5V ± 0.2V 4.5
nS
2.7V 2.5
nS
3.3V ± 0.3V 2.5
nS
RCLR high (inactive) before RCLK↑ 1.8V ± 0.15V 5.5
nS
2.5V ± 0.2V 4.5
nS
2.7V 2.5
nS
3.3V ± 0.3V 2.5
nS
tH Hold time SER after SRCLK↑ 1.2V ± 0.1V 6 nS
1.5V ± 0.12V 2.0
tH Hold time SER after SRCLK↑ 1.8V ± 0.15V 2.0 nS
2.5V ± 0.2V 2.0
2.7V 2.0
3.3V ± 0.3V 1.5