SCDS114E December   2002  – September 2026 SN74CB3Q3384A

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Description
  4. 3Pin Configuration and Functions
  5. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics
    6. 4.6 Switching Characteristics
  6. 5Parameter Measurement Information
  7. 6Device and Documentation Support
    1. 6.1 Documentation Support
    2. 6.2 Receiving Notification of Documentation Updates
    3. 6.3 Support Resources
    4. 6.4 Trademarks
    5. 6.5 Electrostatic Discharge Caution
    6. 6.6 Glossary
  8. 7Revision History
  9. 8Mechanical, Packaging, and Orderable Information

2 Description

The SN74CB3Q3384A is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q3384A provides an optimized interface solution ideally suited for broadband communications, networking, and data-intensive computing systems.

The SN74CB3Q3384A is organized as two 5-bit bus switches with separate output-enable (1 OE, 2 OE) inputs. It can be used as two 5-bit bus switches or as one 10-bit bus switch. When OE is low, the associated 5-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 5-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging current backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE must be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Package Information
TAPACKAGE(1)PACKAGE SIZEPART NUMBER
–40°C to 85°CDBQ(24, QSOP)8.65mm × 6mmSN74CB3Q3384A
PW(24, TSSOP)7.8mm × 6.4mm
DGV(24, TVSOP)5mm × 6.4mm
(1) For more information, see Section 8.
SN74CB3Q3384A Logic Diagram (Positive Logic)Logic Diagram (Positive Logic)
SN74CB3Q3384A Simplified Schematic, Each FET Switch (SW)Simplified Schematic, Each FET Switch (SW)