SCES213Y
April 1999 – August 2026
SN74LVC1G02
PRODUCTION DATA
1
2
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Switching Characteristics, CL = 15pF
5.7
Switching Characteristics, –40°C to 85°C
5.8
Switching Characteristics, –40°C to 125°C
5.9
Operating Characteristics
5.10
Typical Characteristics
6
Parameter Measurement Information
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Balanced CMOS Push-Pull Outputs
7.3.2
Partial Power Down (Ioff)
7.3.3
Standard CMOS Inputs
7.3.4
Clamp Diode Structure
7.3.5
Over-Voltage Tolerant Inputs
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.1.1
Power Considerations
8.2.1.2
Input Considerations
8.2.1.3
Output Considerations
8.2.2
Detailed Design Procedure
8.2.3
Application Curves
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Documentation Support
9.1.1
Related Documentation
9.2
Receiving Notification of Documentation Updates
9.3
Support Resources
9.4
Trademarks
9.5
Electrostatic Discharge Caution
9.6
Glossary
50
10
Revision History
11
Mechanical, Packaging, and Orderable Information
1
Features
Available in the ultra-small 0.64mm
2
package (DPW) with 0.5mm pitch
Supports 5V V
CC
operation
Inputs accept voltages to 5.5V
Provides down translation to V
CC
Maximum t
pd
of 3.6ns at 3.3V
Low power consumption, 10μA maximum I
CC
±24mA output drive at 3.3V
I
off
supports live insertion, partial-power-down mode, and back-drive protection
Latch-up performance exceeds 100mA per JESD 78, Class II