SCES467E July   2003  – August 2026 SN74LVC1G126-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Operating Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS 3-State Outputs
      2. 7.3.2 Partial Power Down (Ioff)
      3. 7.3.3 Standard CMOS Inputs
      4. 7.3.4 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information Disclaimer
    2. 8.2 Application Information
    3. 8.3 Typical Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
      3. 8.3.3 Application Curves
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.4 Thermal Information

THERMAL METRIC(1) SN74LVC1G126-Q1 UNIT
DBV DRY
5 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 357.1 279.0 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 263.7 182.7 °C/W
RθJB Junction-to-board thermal resistance 264.4 154.5 °C/W
ψJT Junction-to-top characterization parameter 195.6 31.3 °C/W
ψJB Junction-to-board characterization parameter 262.2 153.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance – – °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.