SCLS420H June   1998  – January 2025 SN54AHCT123A , SN74AHCT123A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Description
  4. 3 Pin Configuration and Functions
  5. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics
    6. 4.6 Timing Requirements
    7. 4.7 Switching Characteristics
    8. 4.8 Operating Characteristics
    9. 4.9 Input/Output Timing Diagram
  6. 5 Parameter Measurement Information
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 CMOS Schmitt-Trigger Inputs
      2. 6.3.2 TTL-Compatible CMOS Inputs
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Caution in Use
      2. 7.1.2 Power-down Considerations
      3. 7.1.3 Output Pulse Duration
      4. 7.1.4 Retriggering Data
    2. 7.2 Power Supply Recommendations
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
      2. 7.3.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.1.4 Retriggering Data

The minimum input retriggering time (tMIR) is the minimum time required after the initial signal before retriggering the input. After tMIR, the device retriggers the output. Experimentally, it also can be shown that to retrigger the output pulse, the two adjacent input signals should be tMIR apart, where tMIR = 0.30 × tw. The retrigger pulse duration is calculated as shown in Figure 7-2.

SN54AHCT123A SN74AHCT123A Retrigger Pulse Duration Figure 7-2 Retrigger Pulse Duration

The minimum value from the end of the input pulse to the beginning of the retriggered output should be approximately 15 ns to ensure a retriggered output (see Figure 7-3).

SN54AHCT123A SN74AHCT123A Input/Output Requirements Figure 7-3 Input/Output Requirements
SN54AHCT123A SN74AHCT123A Output Pulse Duration vs External Timing Capacitance Figure 7-4 Output Pulse Duration vs External Timing Capacitance
SN54AHCT123A SN74AHCT123A Variations in Output Pulse Duration vs Temperature Figure 7-5 Variations in Output Pulse Duration vs Temperature
SN54AHCT123A SN74AHCT123A Minimum Trigger Time vs vCC Characteristics Figure 7-6 Minimum Trigger Time vs vCC Characteristics
SN54AHCT123A SN74AHCT123A Output Pulse-duration Constant vs Supply Voltage Figure 7-7 Output Pulse-duration Constant vs Supply Voltage
SN54AHCT123A SN74AHCT123A External Capacitance vs Multiplier Factor Figure 7-8 External Capacitance vs Multiplier Factor
SN54AHCT123A SN74AHCT123A Distribution of Units vs Output Pulse Duration Figure 7-9 Distribution of Units vs Output Pulse Duration