SCLS420H June   1998  – January 2025 SN54AHCT123A , SN74AHCT123A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Description
  4. 3 Pin Configuration and Functions
  5. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics
    6. 4.6 Timing Requirements
    7. 4.7 Switching Characteristics
    8. 4.8 Operating Characteristics
    9. 4.9 Input/Output Timing Diagram
  6. 5 Parameter Measurement Information
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 CMOS Schmitt-Trigger Inputs
      2. 6.3.2 TTL-Compatible CMOS Inputs
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Caution in Use
      2. 7.1.2 Power-down Considerations
      3. 7.1.3 Output Pulse Duration
      4. 7.1.4 Retriggering Data
    2. 7.2 Power Supply Recommendations
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
      2. 7.3.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

1 Features

  • Inputs are TTL-voltage compatible
  • Schmitt-trigger circuitry on A , B, and CLR inputs for slow input transition rates
  • Edge triggered from active-high or active-low gated logic inputs
  • Retriggerable for very long output pulses
  • Overriding clear terminates output pulse
  • Latch-up performance exceeds 100mA per JESD 78, class II